sb0 changed the topic of #m-labs to: https://m-labs.hk :: Mattermost https://chat.m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<sb0> so I'm trying to run rust code as kernel, e.g.
<sb0> compile with rustc --target or1k-unknown-none -g -C target-feature=+mul,+div,+ffl1,+cmov,+addc rustkernel.rs
<sb0> or1k-linux-ld -shared --eh-frame-hdr -L . -l :librustkernel.rlib rustkernel.elf
<sb0> but then artiq_run fails with
<sb0> artiq.coredevice.comm_kernel.LoadError: cannot load kernel: parse error: incorrect relocation entry size
<sb0> whitequark: any idea why this doesn't work, off the top of your head?
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<whitequark> sb0: run objdump -p
<whitequark> on the binary
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<whitequark> sb0: oh
<whitequark> sb0: also, it will not work
<whitequark> you need #[no_mangle] on all those extern symbols
<whitequark> and the static mut NOW should be pub
<sb0> whitequark: what about sym_ent above in the firmware?
<sb0> whitequark: yeah there are a few things to polish
<whitequark> why would anything need to be done with sym_ent?
<whitequark> you don't have any rela relocations in that binary, but you can't have a binary without symbols
<sb0> ok
<whitequark> also if you make NOW pub then it'll go away anyway
<sb0> whitequark: okay that works, thanks!
<sb0> do you want to commit it?
<whitequark> done
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<mtrbot-ml_> [mattermost] <sb10q> @astro are you absolutely certain that the MMU is required to use Ethernet on Zynq? Chris went quite far (only ARTIQ though) without messing with it AFAIK
<mtrbot-ml_> [mattermost] <sb10q> why do you need unaligned accesses?
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<_whitenotifier-3> [nmigen] whitequark closed pull request #104: Clean up Xilinx platform code - https://git.io/fj2je
<_whitenotifier-3> [m-labs/nmigen] whitequark pushed 3 commits to master [+0/-0/±7] https://git.io/fja6k
<_whitenotifier-3> [m-labs/nmigen] whitequark 8b34602 - vendor.xilinx_{7series,spartan6}: connect FCDE and IOB directly.
<_whitenotifier-3> [m-labs/nmigen] whitequark 2a8e7bc - vendor.xilinx_{7series,spartan6}: cleanup. NFC.
<_whitenotifier-3> [m-labs/nmigen] whitequark 3fc5f17 - vendor.xilinx_{7series,spartan6}: emit IBUF/OBUF explicitly.
<_whitenotifier-3> [nmigen] whitequark deleted branch xilinx-cleanup - https://git.io/fhUU5
<_whitenotifier-3> [m-labs/nmigen] whitequark deleted branch xilinx-cleanup
<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/546825979?utm_source=github_status&utm_medium=notification
<_whitenotifier-3> [nmigen] Success. 80.71% remains the same compared to 70bbfec - https://codecov.io/gh/m-labs/nmigen/commit/3fc5f170e6a81396adf3e1d72676f55fd0534dee
<_whitenotifier-3> [nmigen] Success. Coverage not affected when comparing 70bbfec...3fc5f17 - https://codecov.io/gh/m-labs/nmigen/commit/3fc5f170e6a81396adf3e1d72676f55fd0534dee
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<_whitenotifier-3> [nmigen] jfng opened pull request #106: vendor.xilinx_7series: fix IOB packing. - https://git.io/fjaP5
<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/546879155?utm_source=github_status&utm_medium=notification
<_whitenotifier-3> [nmigen] codecov[bot] commented on pull request #106: vendor.xilinx_7series: fix IOB packing. - https://git.io/fjaXm
<_whitenotifier-3> [nmigen] Success. 80.71% remains the same compared to 3fc5f17 - https://codecov.io/gh/m-labs/nmigen/compare/3fc5f170e6a81396adf3e1d72676f55fd0534dee...fa7359c5d8fd4d5490caba309fafcab6f76cdbe9
<_whitenotifier-3> [nmigen] Success. Coverage not affected when comparing 3fc5f17...fa7359c - https://codecov.io/gh/m-labs/nmigen/compare/3fc5f170e6a81396adf3e1d72676f55fd0534dee...fa7359c5d8fd4d5490caba309fafcab6f76cdbe9
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<_whitenotifier-3> [nmigen] whitequark closed pull request #106: vendor.xilinx_7series: fix IOB packing. - https://git.io/fjaP5
<_whitenotifier-3> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fjaye
<_whitenotifier-3> [m-labs/nmigen] jfng b3c5ff7 - vendor.xilinx_7series: fix IOB packing.
<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/546949102?utm_source=github_status&utm_medium=notification
<_whitenotifier-3> [nmigen] Success. 80.71% remains the same compared to 3fc5f17 - https://codecov.io/gh/m-labs/nmigen/commit/b3c5ff7e95c768733e681967c0c0aa95d309f2b1
<_whitenotifier-3> [nmigen] Success. Coverage not affected when comparing 3fc5f17...b3c5ff7 - https://codecov.io/gh/m-labs/nmigen/commit/b3c5ff7e95c768733e681967c0c0aa95d309f2b1
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<mtrbot-ml_> [mattermost] <astro> @sb10q here's the artiq-zynq page table: https://github.com/cjbe/artiq-zynq/blob/master/firmware/runtime/translation_table.S
<mtrbot-ml_> [mattermost] <astro> @sb10q loaded here: https://github.com/cjbe/artiq-zynq/blob/master/firmware/runtime/startup.S#L114
<mtrbot-ml_> [mattermost] <astro> I have really tried hard and for too long to go without mmu
<mtrbot-ml_> [mattermost] <astro> vaguely related: I wish we could build nightly rust from its source repo, possibly with some experimental patches
<mtrbot-ml_> [mattermost] <astro> then it might be possible to disable unaligned access in a rust/llvm target definition
<mtrbot-ml_> [mattermost] <sb10q> so the source of the issue is rust/llvm does unaligned accesses and this requires a MMU? Why is it not a problem on the stm32?
<mtrbot-ml_> [mattermost] <sb10q> @hartytp is there any clear technical advantage to sensors like the ad590 (seems to be what many people are using) in a ECDL or can I just use a low cost thermistor?
<mtrbot-ml_> [mattermost] <astro> different target triple
<mtrbot-ml_> [mattermost] <astro> I have just tried with one that includes features: +strict-align
<mtrbot-ml_> [mattermost] <astro> fails in other ways now, investigating...
<mtrbot-ml_> [mattermost] <sb10q> Well the correct way is the path of least resistance, MMU or compiler patch
<mtrbot-ml_> [mattermost] <sb10q> if we turn on the MMU will it get in the way later e.g. when trying to interface with the FPGA design?
<mtrbot-ml_> [mattermost] <astro> ...nope, problems at unaligned access again
<mtrbot-ml_> [mattermost] <astro> I'm reproducing this one in a readable way: https://github.com/cjbe/artiq-zynq/blob/master/firmware/runtime/translation_table.S#L100
<mtrbot-ml_> [mattermost] <sb10q> can't we just compile with the stm32 target triple?
<mtrbot-ml_> [mattermost] <astro> might work, but it would just not be right, right?
<mtrbot-ml_> [mattermost] <astro> the compiler will apply the wrong optimizations
<mtrbot-ml_> [mattermost] <sb10q> also is the MMU reducing performance in any way? Those unaligned accesses sound like they would take multiple bus cycles instead of one
<mtrbot-ml_> [mattermost] <astro> we'd never shoot down the TLB
<mtrbot-ml_> [mattermost] <sb10q> OK do it's just loaded once at startup and stays in the processor core?
<mtrbot-ml_> [mattermost] <astro> exactly
<mtrbot-ml_> [mattermost] <sb10q> OK, that sounds acceptable
<mtrbot-ml_> [mattermost] <sb10q> And it's just a TLB for the CPU core, right? There is no funny business with the FPGA interfacing
<mtrbot-ml_> [mattermost] <astro> it's no IOMMU
<mtrbot-ml_> [mattermost] <astro> really just in the CPU core
<mtrbot-ml_> [mattermost] <sb10q> Ok
<mtrbot-ml_> [mattermost] <sb10q> why is llvm doing those unaligned accesses in the first place? They do seem slow. Or is the CPU cache good at handling them or something?
<whitequark> making unaligned accesses in software is also slow
<whitequark> since you need more instructions
<mtrbot-ml_> [mattermost] <astro> they happen when I read the u8s in a mac address `[u8; 6]`
<mtrbot-ml_> [mattermost] <astro> they happen in some clever optimization for printing decimal numbers in core::fmt
<whitequark> unaligned access into dcache is 2 cycles max, but if you do this with instructions i think you need a shift and a mask, which is worse
<mtrbot-ml_> [mattermost] <astro> it's really hard to eliminate them all over the place
<mtrbot-ml_> [mattermost] <astro> I would have hoped to avoid them by target spec, but no
<mtrbot-ml_> [mattermost] <sb10q> yeah sure, I get that if you do need an unaligned access then doing it in hardware is faster, but I'm surprised they are needed
<whitequark> unaligned accesses are required each time you have a packed data structure
<whitequark> which happens each time you have an array of anything under a word size
<mtrbot-ml_> [mattermost] <sb10q> Hmm yes, but what is often done here is to align each member of the structure
<mtrbot-ml_> [mattermost] <astro> you'll optimize that in the paths that have to be fast
<mtrbot-ml_> [mattermost] <astro> today I have tried to get a `#[repr(align(16384))]` but it just won't work although it is supposed to do up to 2^31. it would have been prettier than doing it by linker script.