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<oliv3r>
eva got back with me
<oliv3r>
i got in her spam box :(
<mripard_>
so, what was the answer?
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<wens>
mripard_: wow, the mmc clock is complicated
<mripard_>
not that much actually
<mripard_>
but the code is :)
<wens>
i'll look through it if my headache (not related) lessens
<mripard_>
you actually have 3 clocks
<mripard_>
a mod0 one, that is output directly on the SD card
<mripard_>
but since there's some delay between the clock output and the SD, you have to out-phase the two other clock that we provide, that are the output clock, that is used by the controller to output data on the bus, and the sample clock, to sample data from the bus
<mripard_>
0 in the phase register means out phased by 180 deg.
<mripard_>
1-7 is the delay you want to outphase the clocks from, the unit being a period of the parent clock
<mripard_>
so PLL6, most likely
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<wens>
you got this info from aw engineers?
<mripard_>
yep
<mripard_>
finally...
<wens>
a fine example of why datasheets shouldn't be just register definitions
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<mripard_>
yep....
<montjoie[home]>
I read that A80 will not have datasheet, does it true?
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<mripard_>
montjoie[home]: I don't know ...
<mripard_>
but it's not the only one
<mripard_>
a10s and a31 don't either
<wens>
merrii released android 4.4 sdk for a31 hummingbird
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<Net147>
http://linux-sunxi.org/Fex_Guide - added screen0_out_color_range under [disp_init] for setting HDMI color range. apparently it isn't using the full color range by default... it uses 16-255 instead of 0-255.
<Net147>
I couldn't find it documented anywhere
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<arete74_>
ssvb_: hi, is possible use with cubieboard2 ?
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<dack>
I'm trying to get the script.bin off of a device but am having issues... I tried accessing /dev/block/nanda through Android and there's no script.bin in there! There's also no uboot or kernel... I don't get it.
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<libv>
oliv3r: hrm, has my blogpost had some effect, or is this all just coincidence?
<libv>
"it landed in my spam folder" smells like "my dog ate my homework"
<libv>
especially since a lot of stuff must've been hitting evas spam folder in the last few months
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<FergusL>
Turl: reading this wiki, but it doesn't explain how to build u-boot, the BSP wiki is the right way ? :s
<Turl>
FergusL: if you use the bsp that way you should be fine
<FergusL>
ok
<Turl>
but you said you downloaded one, which may be ancient
<wens>
Turl: didn't have any
<Turl>
wens: ah ok :)
<Turl>
wens: if you want to play with it again, mono & 24b audio work now
<wens>
might not get time until next week
<ssvb>
jemk: there is also a cold start problem, potentially resulting in a somewhat different zq calibration outcome
<jemk>
ssvb: no, dcdc3 is 1.3V, as u-boot sets it
<FergusL>
Turl: the hwpack I dled has u-boot.bin and sunxi-spl.bin in the bootloader/ folder, but I can't find it in the SD card that media-create created. Is that nrmal ? shouldsn't these files be in the boot partition ?
<Turl>
FergusL: those files are dd'ed to the card directly, but they are old, it's been a while since uboot doesn't build those anymore
<Turl>
so make a fresh one
<FergusL>
Turl: ok... I hope I can find a solution, my goal is : Ubuntu 14.04 with a realtime kernel. I built the kernel folliwing the wiki page for this. But then I can't find a recent ubuntu version for sd cards. So I found BSP, I tried to make a media, but it didn't work, I modified an hwpack but ddn't work. so I ran ./configure cubieboard2 and then make which should create an hwpack, let's hope media-create will work when all this is done !
<FergusL>
right now it's cloning the full sunxi repo, duh !
<FergusL>
it's going to compile a full kernel actually... right ?
<ssvb>
jemk: the dark green table cells mean that the tpr3 value is confirmed by a much longer test, light green color means a failure on a longer confirmation test run
<Turl>
ssvb: are you becoming a dangerous OCer? :)
<ssvb>
jemk: and our boards already had somewhat different behaviour in the top left corner, when tested earlier without ODT tweaks
<jemk>
ssvb: yes, I'll try to run a tpr3 scan with your new u-boot next days
<ssvb>
jemk: ok, thanks
<jemk>
ssvb: eta for tpr3 scan?
<oliv3r>
anything i can test on a few limes?
<ssvb>
jemk: maybe 5-6 hours, but now it is more clever and starts searching around the original tpr3 from u-boot
<ssvb>
jemk: so you get the most interesting results reasonably fast
<ssvb>
oliv3r: nah, only cubietruck so far
<jemk>
ssvb: ok, thats good
<ssvb>
oliv3r: and a10-lime keeps changing zq resistor nominals in every revision :( that's a pretty bad choice for experiments
<ssvb>
jemk: could you paste the a10-meminfo log?
<oliv3r>
ssvb: i got one of those too
<oliv3r>
ssvb: and i have a lot of revC boards :p
<oliv3r>
ssvb: and we'll likly switch to a20 lime
<oliv3r>
price diff is negiable
<ssvb>
jemk: now it reports something like "dram_zq = 0x2c (0x10d3900)", where 0x2c is the ZPROG value, which gets translated into 0x10d39 ZDATA after calibration
<ssvb>
jemk: I wonder if you get the same or different numbers
<oliv3r>
ssvb: anyway, if you want me to run some test or something, i can do stuff
<dack>
Alright.. I recompiled my kernel for my MK808C with the sunxi_nand built in. I manually created a /dev/nanda with mknod and tried mounting it. I now have a 'nandd' process going at 100% cpu and the shell that tried to do the mount is unresponsive. wtf?
<dack>
k.. restarted.. seems nandd is running at 100% without creating node or trying to mount it.
<ssvb>
jemk: 0x10d1800 is what I'm getting on a cold start, and 0x10d3900 after the board has worked for a while and has heated up
<ssvb>
jemk: these are 4 packed values, 5 bits for each
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<ssvb>
jemk: ignore the lowest 00 byte (it is reserved for ZPROG)
<ssvb>
jemk: it looks like the zq calibration results are mostly the same on our boards, so an interesting question is whether it would be a good idea to configure ZDATA instead of ZPROG
<jemk>
ssvb: board is pretty warm, 25C ambient and powered on since ~4h
<ssvb>
jemk: you may get something entirely different on a cold start, after letting it to cool down for maybe ~5 minutes after power off
<jemk>
ssvb: doesn't zq calibration have to be redone sometimes
<ssvb>
jemk: it does not have, but it is surely a good idea
<ssvb>
jemk: for the DDR3 chip, re-calibration is supposedly done at the same time as refresh, but the DRAM controller needs to do it explicitly via ZQCS command
<ssvb>
jemk: and this is something that I have no idea how to verify
<oliv3r>
ssvb: its rebooting, lets hope it comes back :)
<ssvb>
jemk: as the ZCTRL value in SDR_ZQSR register remains the same after boot, I assume that the periodic re-calibration is not done automatically there
<ssvb>
jemk: I mean, I do a cold boot, get 0x10d18 in SDR_ZQSR and it just stays there
<ssvb>
jemk: then I reboot the system without letting it to cool down, get 0x10d39 and it also stays there until the next reboot
<jemk>
ssvb: or zqcs isn't as accurate as the long zqc
<ssvb>
jemk: ZACL and ZQCS happens in the DDR3 chip and affects the side of the PCB tracks, which connects to the DDR3 chip
<ssvb>
*ZQCL
<ssvb>
jemk: but the SDR_ZQCR0/SDR_ZQSR deal with the impedance on the side of the PCB tracks, which connects to the SoC
<ssvb>
jemk: they even use different ZQ resistors (one is connected to the SoC, and one is connected to the DRAM chip)
<oliv3r>
ssvb: bah, board didn't come back up; i'll check later don't have uart nearby
<oliv3r>
maybe things crashed due to FAST_MBUS :(
<ssvb>
oliv3r: oh, sorry about that
<oliv3r>
ssvb: it's no problem, what's the best way to make your u-boot boot
<oliv3r>
on my 'weird' cb3
<ssvb>
oliv3r: write it to the sd card?
<oliv3r>
i did that lol
<oliv3r>
i mean can I just disable FAST_MBUS
<oliv3r>
and still help testing for you
<ssvb>
oliv3r: there is no FAST_MBUS anymore, just "clock" and "mbus_clock"
<ssvb>
oliv3r: you can set "mbus_clock" to 300
<oliv3r>
ah you split it up in dram settings, ok
<ssvb>
oliv3r: and maybe reduce "clock" to something more reasonable, like 528, 480 or 432
<oliv3r>
will it affect your test?
<ssvb>
oliv3r: well, it appears that my test has failed already on your board :)
<oliv3r>
lol
<oliv3r>
i'll check in a minute what went wrong
<oliv3r>
oh wait, i can't, i'll have to reset to try again :p
<oliv3r>
i'll do that in amin
<jemk>
ssvb: bwdsp manual says zqcr0[30]: "NOICAL, initialization impedance calibration control. When this bit is set, then the DDR2 controller does not perform automatic impedance matching operation in the initialization time, otherwise, the controller automatically performs impedance matching operation during initialization."
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<ssvb>
jemk: this seems to talk about the initialization time, and not about the periodic correction at runtime
<ssvb>
jemk: zq calibration works fine at the initialization time, as can be seen by tweaking the settings (some settings are clearly better than the others)
<ssvb>
jemk: does the bwdsp manual mention anything about ZQCS and period between ZQCS?
<oliv3r>
ssvb: hmm, i just got a ram error, please reset board; but i recompiled with lower timings, lets see what happens now
<ssvb>
oliv3r: you can also try to tweak the 'dqs_gating_delay' parameter (set it to 0 for auto-detection, and also check 0x06060606)
<jemk>
ssvb: zqcr1 looks good, but google translate produces bullshit
<ssvb>
oliv3r: this used to be a problem on your board earlier
<jemk>
ssvb: 26:24 is reserved, but 30:28 says CALTYPE, 001 = "When calibration is performed automatically refresh (google translate)" and 31 CALEN 1= perform auto impedance matching
<oliv3r>
ssvb: ok i'll experiment more on a later time
<oliv3r>
ssvb: it failed now with mmc read error blk0
<ssvb>
oliv3r: error in u-boot?
<oliv3r>
yeah
<oliv3r>
i'll test a known working u-boot on the mmc at a later time
<oliv3r>
btw, i only have /boot on sd card, rootfs is on an ssd
<ssvb>
ok, thanks
<ssvb>
jemk: this description makes sense, at least it appears to be quite common to issue ZQCS commands (and sometimes also ZQCL) to let the DDR3 chip re-calibrate itself during refresh
<jemk>
oliv3r: be carefull, some ssds dont like too many hard resets
<jemk>
ssvb: some things sound strange and could also be the other way around, i can't read chinese
<ssvb>
jemk: yes, still the biggest problem is that we very likely can't really verify whether this all works by using just the software methods
<ssvb>
jemk: this is a one way communication from the DRAM controller to the DDR3 chip
<ssvb>
jemk: and we have no idea if the calibration at the initialization time is good enough or actually needs correction
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<ssvb>
jemk: I have some ideas about how to interpret this and maybe will try some tests later
<ssvb>
jemk: the mysterious bit 24 in the SDR_ZQCR1 on A20 might have something to do with ZQCSB from bwdsp "1 = Do not send commands to the SDRAM when ZQCS impedance calibration"
<ssvb>
jemk: by setting it to 1, we are disabling something that otherwise deadlocks the system
<jemk>
ssvb: but thats bit 27. I thougt it might be simply some extension placed in the reserved area
<ssvb>
jemk: the four bits 24-27 in A20 behave like they are read-only (read back as 0), but writing 1 to bit 24 is necessary
<jemk>
ssvb: i mean, bwdsp is much older, only ddr2 and so on
<ssvb>
jemk: the bit 27 is just on the opposite side of this group of bits
<ssvb>
jemk: in any case, the difference in optimal settings between our boards is unlikely to be zq related
<ssvb>
jemk: we might try to find some intersection of good settings, and a safe clock speeds range that works everywhere
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<ssvb>
oliv3r: have you tried the mainline u-boot on your cubietruck (other than the one with my patches)? we would need your board to ensure that everything is fine
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<jemk>
ssvb: yes, sure. I will run some tests as soon as possible, but i first need to change some things, ct runs pretty productive at the moment, can't risk destroying the filesystem or even the whole harddisk with all those hard resets
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<ssvb>
jemk: what I mean is that the temperature induced differences in the impedance settings are rather minor at least for me
<ssvb>
jemk: it does not look like fast DRAM clock speed has much use without fast MBUS on the systems with 32-bit memory interface
<ssvb>
jemk: but some cedarx benchmarks would be interesting too
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<Black_Horseman>
meres
<jemk>
ssvb: I want to figure out something about cedar memory access patterns, caches, bursts and so on since ages, but never had time to intensively try it
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<jemk>
ssvb: anyway, i'm out for today, lets see what scan-tpr3 will reveal.
<jemk>
bye
<ssvb>
ok, see you later
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