<ssvb>
mnemoc: but appears that linux-sunxi has been forked 268 times on github by itself and the github network graph for it is still rather heavyweight :)
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<punith>
in allwinner pack tools where uImage is get located in out folder
<punith>
for packing in linux only not android
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<lauri>
Morning guys
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<plaes>
lauri: o/
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<lauri>
plaes: Hola, veedad siin ka aega jah? :P
<plaes>
jap
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<lauri>
How would one configure MOSI/MISO ports on CT?
<lauri>
That's the SPI port right
<lauri>
The spi0 port is disabled by default in FEX config, are those pins used for anything else?
<lauri>
Can I assume that most pins are by default in the GPIO mode?
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<libv>
heh, pcduino v3 support, straight in dts
<libv>
no .fex or nothing.
* libv
hates pointless and useless fragmentation: it will come back to bite us seriously up the ass, like the a20 tablet usb situation atm.
<libv>
a20 tablet usb will never work on mainline, and no-one cares.
<ccaione>
why will never work?
<libv>
because of fragmentation, and the fact that no-one can be arsed to work on anything but development boards for mainline.
<libv>
as i stated back in... november?
<libv>
this reduces linux-sunxi to equal or below other soc projects.
<libv>
and throws away the big advantage of the sunxi platform
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<ccaione>
well, you start from dev boards and eventually tablet and such
<libv>
like that will ever happen.
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<libv>
mainline will be 99% dev boards.
<libv>
and it now has come to this as well.
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<libv>
devboards will only work, and partially work, on mainline
<libv>
and no-one can be arsed to run it against sunxi-3.4
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<ccaione>
we will see, but I have hope that once we have all the pieces in mainline, people will start mainlining also !devboards
<wigyori>
libv: fully agree on the lack of docs for the pcd v3, i'll do that. for u-boot, i'm working on the patchset to be pushed in. for the .fex file, i can gather that from the vendors
<libv>
ccaione: "once"?
<ccaione>
we are getting closer
<libv>
ccaione: what is the time difference between a SoC shipping and all pieces being in mainline?
<libv>
ccaione: in that time, people will have resigned to the facts of life.
<libv>
and cannot be arsed anymore afterwards.
<wigyori>
for the mainline/3.4 split or fragmentation, you see how guys are split - my side is pushing for mainline
<ccaione>
when you have all the generic / general components (axp, usb, mmc, ) in mainline the time difference can be also small IMO since you already have a code base to work on
<libv>
it will play out as i just stated.
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<libv>
unless i of course whine/kick arse enough, but i believe that i have spent enough time on that and related work with linux-sunxi
<ccaione>
:)
<libv>
and what wigyori just pulled is just another big middle finger to me and my views.
<dw>
does upstream even want to support so many variants of the same hardware?
<wigyori>
looks like i've kicked the hornet's nest unintentionally
<libv>
we've entered the next stage of fragmentation
<libv>
and should really just declare that linux-sunxi is two different projects
<libv>
one for devboards, and one dying one for getting a proper OS on an android device
<libv>
dw: it would be interesting to submit 70 automatically converted .fex files for upstreaming.
<libv>
will give them something to think about, with their "the one true way" thinking
<dw>
i thought the .dex->dts thing was going to be a boot time hack :) guess i wasn't paying enough attention
<libv>
dw: hrm, so it's an excuse to no longer have to think about it?
<libv>
a small concession to silence my concerns?
<libv>
and to ignore the grand scheme of this problem?
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<libv>
wow, completely broken encoding, which started from the allwinner source dump :(
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<libv>
so all the chinese comments are a useless diff
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<libv>
a23 sdk btw
<libv>
how one succeeds at that is beyond me.
<mnemoc>
libv: they do mix encodings a lot
<libv>
the valid unicode characters seem to have been mostly replaced with 0xbdbfef
<libv>
wigyori: did you make the main device picture of the pcduino?
<libv>
it's a different camera and it was created in march
<libv>
wigyori: i will need to go in detail on this page again, you for instance removed too many categories.
<wigyori>
libv: not the main one, but the front and back
<wigyori>
same for the pcduino v1/v2 pictures
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<libv>
where did you get the main one?
<wigyori>
linksprite website
<libv>
so you had no right to put this on the wiki.
<libv>
this sort of thing is explained several times in our wiki.
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<libv>
*sigh*
<wigyori>
yea, that's removed now
<libv>
amazing.
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<libv>
wigyori: do you work for linksprite?
<libv>
there's not a detail that can be trusted.
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<Turl>
libv: I thought babelfish was going to cover up for the lack of non devboards?
<wigyori>
libv: no. that's getting to be a bit too much heat. i pushed these two boards into openwrt, then wanted to get these upstream.
<wigyori>
libv: you can tell me to fuck off, but accusing me of things is another story
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<jukivili>
ccaione: no, not really
<libv>
wigyori: i am not "accusing" you of working for a vendor, i don't care whether you work for a vendor or not
<libv>
you just have several pcduino devices, and you make a very sloppy job of the wiki.
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<montjoie[home]>
i am stunned by the bad performance of the a20 security system
<popolon>
Just seen than every other languages than english was removed from the wiki ?
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<popolon>
DOn't understand why for ? That's not like this other few text taken lot of ressources
<Wizzup>
montjoie[home]: someone got the security system to work?
<montjoie[home]>
Wizzup yes me:)
<Wizzup>
cool
<Wizzup>
What is "bad performance"
<Wizzup>
?
<montjoie[home]>
you do not loose performance only with AES256 and in that case the gain is at maximum 10%
<Wizzup>
compared to plain cpu?
<montjoie[home]>
in other AES (128 / 192) the gain is negative up to 50% loss
<Wizzup>
and it's not like, related to the driver being in it's initial states?
* Wizzup
is overly curious
<montjoie[home]>
yes compared with neon implementation
<montjoie[home]>
I expect better perf when DMA would be availlable
<Wizzup>
Ah...
<Wizzup>
Yeah, that'll matter :
* Wizzup
is looking into looking small tor exit nodes
<Wizzup>
that... sentence broken down
* Wizzup
is looking into creating small arm,based, tor exit nodes
<montjoie[home]>
but for my initial target case (cryptsetup) security system is bad
<Wizzup>
Ah
<Wizzup>
still, it's progress :)
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<montjoie[home]>
since Security System does not support AES XTS mode
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<Wizzup>
The A10 also has security system, right?
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<hypothalamus>
montjoie[home]: do you know if security system will speed up openssl?
<montjoie[home]>
Wizzup yes
<Wizzup>
hypothalamus: probably with DMA, I guess
<montjoie[home]>
hypothalamus as I said, for AES only when using 256bits key and maximum gain is 10%
<montjoie[home]>
with the 3,4 kernel, the DMA was usefull only for request > 4k
<hypothalamus>
so these values are not relates to cryptosetup only? how about hashes?
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<montjoie[home]>
I developping a benching kernel module for comparing with crypsetup, for the moment simlilar values
<montjoie[home]>
for sha1/md5 I need to redo my bench
<hypothalamus>
ok - thx for your effort
<montjoie[home]>
but a small gain is possible
<Turl>
you also need to account your cpu can do other stuff while the SS is doing the job
<Turl>
so systems may be more responsive and such even if the overall MB/s perf is slower
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<Wizzup>
Turl: other stuff, like more crypto? ;-)
<montjoie[home]>
one request at a time for security system:)
<hypothalamus>
if i get 10% more throughput and lower CPU usage i'd be happy ;)
<montjoie[home]>
I am not, I dreamed x2:D
<hypothalamus>
well it's better than nothing :P
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<Wizzup>
It may still get higher if you find some bottlenecks :-)
<Wizzup>
(I guess)
<montjoie[home]>
I am near to have tested anything
<Turl>
you can clock SS higher as well
<montjoie[home]>
I failed at that Turl
<Turl>
but too high causes data corruption and you get garbage
<montjoie[home]>
one clock is already at maximum
<Turl>
brb
<montjoie[home]>
maximum as said by the datasheet
<montjoie[home]>
each AES request already have 3 code path different for optimizing
<ssvb>
montjoie[home]: 200MHz?
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<montjoie[home]>
160 for the clock bus
<ssvb>
hmm, the A20 manual says that 200MHz is the limit for SS_CLK_REG
<ssvb>
where did you find 160?
* torindel
dohs
<torindel>
bought olimex A20-OLinuXino-MICRO-4GB + olimex A13-LCD7-TS and got borked 40pin data cable
<wens>
160 is ahb?
<torindel>
kernel always froze (without panic or anything on uart) when loading lcd module on borked cable
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<ssvb>
wens: hmm, and why do we have 160 for ahb?
<ssvb>
wens: the A20 manual says that the supported range of clock frequencies is 8K~276M
<montjoie[home]>
ssvb at the end of ss section oh the manual
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<montjoie[home]>
ssvb page 228
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<ssvb>
montjoie[home]: oh, thanks, I see
<ssvb>
have you tried to oveclock it?
<ssvb>
it's strange that different sections of the manual do not agree with each other
<ssvb>
and also maybe tweak the ahb clock speed as hinted by wens
<montjoie[home]>
ssvb yes I have tried to overclock but failed
<montjoie[home]>
but by default, the driver does not have to overclock
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<ssvb>
montjoie[home]: we just want to know what exactly is limiting the performance. Is it the ss clock speed? Is it the ahb clock speed? Is it just the time for cache flush/invalidate to maintain coherence?
<ssvb>
montjoie[home]: that's why nudging the clock speeds up and down may be interesting
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<montjoie[home]>
ssvb good remarks, I will retry
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<torindel>
out of interest: when getting hard kernel panic does it'll show on uart if console=ttyS0 or not?
<torindel>
(CONFIG_ARCH_SUN7I (A20) if it makes any difference)
<nove>
mripard: If by chance that was a reference caused by me(well i hope was me), then should be "Libre Software Extremists". I am not here to do free work for anyone, if that is being extremist then i am happy to be called as one.
<nove>
mripard: So for next time, i would appreciate if this would be corrected. Too bad it wasn't recorded, for surelly that would be for laughters.
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<nove>
To everyone, if my spit bullshit rants aren't appropriate, then tell me to shutup and i will. But don't stay silent towards the problems that this community is facing.
<nove>
i know, less talking more coding (as seeing talking is going nowhere)
<libv>
but why would this result in a kernel panic?
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<torindel>
libv: dunno, kernel/board just hanged after modprobing lcd
<torindel>
no kernel panic no nothing
<torindel>
hard freeze, network stops working etc
<torindel>
swaped lcd cable to some old 40pin one from hdd drive and it works (it have 40pin connectors on a20 and on that lcd)
<torindel>
wierd that i dont get anything on uart after loading lcd module
<libv>
nothing at all anymore?
<libv>
hrm
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* libv
is in the middle of rewriting some pcduino wiki pages and usb stuff
<libv>
otherwise i could've just fired up my olinuxino hw and checked
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<rds>
libv, could you provide a status of the KMS driver ?
<rds>
I see that you continue to be busy, writing wiki pages.
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<libv>
rds: when did you last ask?
<rds>
about 3 wks ago!
<rds>
here why I am asking:
<rds>
I want to try a mainline linux with grphics support.
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<joga>
I'm trying to get some uart pins working so that I would have a bidirectional /dev/ttySx for interfacing with other hardware (such as gps receiver) over serial, with fresh cubian and A10 cubie, I tried to enable in script.fex the uart_para5 port, but which pin is PH06?
<rds>
and waiting for a good break through on this area with your KMS driver
<joga>
I tried to look at the pinouts but couldn't find it
<libv>
joga: did you find it on the cubieboard schematics?
<rds>
I understand you are doing great!, but shake my head when I see you writing wiki pages. My guess is you are trying to be a book writer!
<libv>
rds: i do what i think needs doing
<libv>
rds: and the last thing i need is someone selfishly telling me what he thinks i should be doing.
<libv>
rds: so fuck off.
<rds>
I am not trying to tell you what to do!
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<rds>
I am asking for the status of the driver!
<libv>
you're only fooling yourself with that statement.
<rds>
I wish I could help, but my skill is only 2 years of Visual Basic and a bit of Java Script.
<joga>
libv, well, yeah, but to be honest tracing the actual physical location from pages of diagrams seemed like too much of a hurdle
<joga>
from this page http://linux-sunxi.org/Cubieboard/ExpansionPorts I see PI10 being referenced as UART5-TX, but I tried configuring that also for uart_para5 as tx, but didn't seem to get anything out of it
<joga>
just wondering if I've overlooked something simple, I do get the ttySx device and I get "[ 2.092258] sunxi-uart.5: ttyS2 at MMIO 0x1c29400 (irq = 18) is a U6_16550A" in dmesg
<libv>
wigyori: i have fixed up all the pages now, please fix the missing bits
<libv>
joga: let me dig through my irclog, i am not sure anymore who was playing with an extra serial port on cubietruck yesterday
<libv>
i think lauri
<libv>
yeah, lauri
<joga>
hmh
<wigyori>
libv: will do, thanks
<joga>
lauri, you around? :)
<libv>
prorocol?
<libv>
let's hope that the chinese who are growing up today have much more exposure to the english language than the guys at allwinner who wrote this code
<physis>
I follow yours tips and after rebuild u-boot I can now boot from sunxi-devel tree. But I it hangs on "Waiting for root device /dev/mmcblk0p2".
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<popolon>
libv, lot of technical stuff have translation in other languages, with wiki or not I don't really understand why there is something about wikipedia ???
<popolon>
and for the second one, that's just to avoid that people that don't read english can't have access to answer
<popolon>
is this about >OPEN< source software, has there is open mind and openness....
<popolon>
For the example that's totally wrong, I first translate, and then added things and put back things, and that's the case in several pages
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<popolon>
and definitively now, the first spoken language is chinese mandarin, not english...
<popolon>
If this only something against me, other people translated in other languages at this time. I really appreciate the comment you made, only against me that my few documentation addition was useless, you really didn't read the chronology at all and write a false statement, this is really sad, I contributed to a lot of open source projects...
<popolon>
bye
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