<whitequark> rqou: no, usb is an example of worse is better
<whitequark> ethernet is p okay overall
<whitequark> i mean, what are your complaints about it
<rqou> i thought ethernet was considered much more primitive than various other network protocols?
<Ultrasauce> we got layers for that shit
<awygle> yeah Ethernet is just well abstracted
<awygle> 800 page standard notwithstanding
<awygle> I have the impression that Tk is garbage, is that generally shared?
<Ultrasauce> is there a ui toolkit that isnt?
<Ultrasauce> serious question
<Ultrasauce> Qt is my favourite but also garbage in its own way
<awygle> not to my knowledge, I'm looking for something that is just a wrapper around the native UI
<mithro> awygle: Correct - avoid Tk if you can
<mithro> awygle: For Python?
<mithro> awygle: I hear good things about Toga -> https://github.com/pybee/toga
<awygle> mithro: currently yes, although if it also worked in C++ and Rust that would be ideal
<awygle> I just found toga
<awygle> It doesn't really support win32
<awygle> I suppose I could fix that... Yakity yak
<mithro> brb
<whitequark> cr1901_modern: avoid the dragon book
<mithro> awygle: Give up on windows is another option? :-P
<whitequark> it's ancient and not really representative of modern parsing tech
<awygle> mithro: is it tho? (it is not)
<rqou> Ultrasauce: yet another "worse is better" suggestion: use a browser? :P
<rqou> not really suitable for what awygle wants though
<rqou> awygle: do you like leaky abstractions? use WX
<awygle> rqou: wx is bad
<awygle> been there done that
<rqou> i know
<rqou> but you seem to really like having native widgets
<awygle> browsers are also bad although at least I'd be more employable that way
<rqou> i did say that browsers are "worse is better"
<awygle> can you even do python browser?
<rqou> yes
<rqou> :P
<awygle> I'd probably have to learn js...
<rqou> O_o
<rqou> i didn't realize somebody had already done this
<gruetzkopf> hm
<awygle> oh no somebody else out there has ideas as bad as rqou
<rqou> bad?
<awygle> I am actually too ignorant to tell whether this would enable what I want to do
<Ultrasauce> PyQt might actually be your best bet if you plan on moving to cpp after prototyping or whatever anyway
<rqou> the biggest problem is still getting maximum performance and poking enough holes to do IO
<rqou> Ultrasauce: licensing :(
<awygle> PyQT isn't bad, I'm not unduly bothered by GPL
<rqou> it mattered the last time i used it
<awygle> Does qt use native widgets though?
<rqou> because it was for BRCM
<rqou> idk, idc
<rqou> i don't care about native/non-native widgets
<rqou> although a11y and IMEs are important
<Ultrasauce> yes I think so
<mithro> rqou: pybee also has another project to crosscompile python to javascript
<rqou> nonono
<rqou> "cross-compilers" all fail in strange ways
<mithro> Oh wait -- sorry
<mithro> Batavia is an implementation of the Python virtual machine, written in JavaScript. With Batavia, you can run Python bytecode in your browser.
<rqou> ah, that's more likely to work correctly
<rqou> but yeah, there are tons of python->JS transpilers
<mithro> rqou: They have a pretty big test suite
<rqou> it is/was a pretty popular "final project" at one point
<rqou> yeah, reimplementing a python VM might actually wor
<rqou> *work
<awygle> hm it appears that qt uses widgets that look native but are not
<rqou> usually i see transpilers that take a lot of shortcuts and fail when you use e.g. metaclasses
<mithro> awygle: Correct - they are frustratingly close and fall into the uncanny valley
<rqou> awygle: can you explain to me why this really matters?
<awygle> rqou: mithro just said it, the uncanny valley. non native apps feel wrong, they don't integrate well with the system, it's just a bad user experience
<rqou> hmm, i guess i just don't expect things to work this way
<awygle> rqou: you don't feel this way because you change platforms a lot and your primary platform is Linux which has never had a platform UI toolkit
<mithro> awygle: The thing is you don't really expect a web app to integrate with the system properly, but something which kind of does look like it should you then get frustrated when things don't work
<awygle> so all Linux gui apps are frustratingly terrible
<awygle> Well not all but lots
<awygle> And yes browsers take the R2-D2 approach
<mithro> R2-D2 approach?
<awygle> Cute and friendly and not even trying to look human
<awygle> The other side of the uncanny valley
<rqou> what about "vidya" custom UIs? :P
<rqou> somehow they all seem to have one
<mithro> So, anyone want to review some schematics for me?
<awygle> mithro: sure
<awygle> What kind
<mithro> FPGA dev boards in KiCad
<mithro> I need to get the schematics into working order so they can be routed...
<awygle> mithro: are you on a particular timeline?
<mithro> awygle: If I say no, will they ever get reviewed? :-P
<awygle> mithro: yes, just possibly not before tomorrow night :-P
<mithro> Like, if you did it in a couple of days that would be more than fast enough
<awygle> Sure, can do
<mithro> awygle: Notice the "Latest commit 99bf3f0 on Feb 4" :-P
<awygle> Any priority order?
<awygle> (I am clearly back to having a boss...)
<mithro> If I can get them into a state were they are suitable for layout, then I have people who are willing to do the PCB layout
<mithro> Probably the (1) negl-a7, (2) clad, (3) zvznf-v2
<awygle> K
<rqou> O_o expensive boards
<rqou> how are you planning to get these manufactured?
<mithro> rqou: Define expensive? They should be $100 USD or less
<rqou> wat
<rqou> with a zynq?
<awygle> Yeah I assume the pynq is heavily subsidized
<awygle> Or at least extremely uh... Voluminous?
<awygle> Not right word even slightly
<mithro> You can get the Zynq in 100 units in the $30-$40 USD price range
<shuffle2> voluptuous
<awygle> volumetric
* awygle noms
<mithro> You can get a Zynq board in the $85 USD BOM cost if you make ~100
<mithro> So, as I'm not trying to make a profit or recover NRE, I can happily sell them for around $100 USD
<rqou> ah that makes a lot more sense
<rqou> since i expected (applying the rule of thumb) $400
<rqou> also because i definitely can't front $4k
<mithro> rqou: $8,500 :-)
<rqou> yup, definitely not fronting that :P
<mithro> Yeah - by the "rule of three" you want at least $250
<rqou> i was using "rule of four"
<rqou> but yeah, since i also have never exercised marketing skills, i wouldn't buy so much up front
<whitequark> "vidya" custom UIs are all godawful
<Ultrasauce> my favourite example is probably crysis embedding flash for the ui
<rqou> would you be more or less unhappy with embedded gecko/webkit?
<Ultrasauce> you drive a hard bargain sir
<rqou> lol
<rqou> so you do hit bikesheds
<Ultrasauce> status:New → Opinion
<whitequark> rqou: hm? what do you mean?
<rqou> isn't the oval discussion basically a silly bikeshed?
<rqou> (i have no opinion either way and don't usually use rounded pads)
<whitequark> i dunno, i find the name confusing, and awygle does too
<rqou> also, f*cking sigrok
<rqou> why does it crash all the time?
* rqou blames USB
<whitequark> are you running trunk?
<rqou> no
<rqou> whatever is in debian sid
<whitequark> oh
<whitequark> well debian has some ancient sigrok
<rqou> wtf
<rqou> i'm really on the verge of dropping debian
<whitequark> technically, i think they have the latest release of sigrok
<whitequark> so it's not the fault of debian
<whitequark> but of sigrok for writing shitty code
<mithro> daveshah: btw I would love you to work on micropython for FPGAs as part of FuPy - https://github.com/fupy - fupy.github.io
<rqou> i just hate dealing with angry germans, broken gui stuff that i don't care about, and not-even-unstable-enough electronics/eda/cad/etc. packages
<balrog> the version in sid is relatively current
<rqou> hmm, i should check if they unfucked okteta yet
<Ultrasauce> oh just to backtrack for a minute there rqou...if you're on debian that probably explains your past problems with gstreamer
<Ultrasauce> downstream package fuckery abound
<rqou> i used to be on ubuntu
<Ultrasauce> worse for that
<rqou> not sure if that helps or not
<whitequark> i've yet to find a distro less shitty than debian tbh
<rqou> arch? the weeb distro
<whitequark> lol arse linux
<whitequark> rolling releases are unusable
<whitequark> really, anything that i can't safely update in cron is unusable
<rqou> huh
<rqou> i purposely switched to a rolling release because i started to find ubuntu unusable
<rqou> every time i upgraded everything stopped working
<whitequark> it's mostly for servers
<rqou> and upgrades would always launch in the middle of the semester during crunch time
<whitequark> the last time debian broke something on my server was like in 2008
<rqou> yes, i run ubuntu on my servers
<whitequark> which was the /dev/sda vs /dev/hda
<rqou> and the last upgrade was a fucking disaster
<rqou> i went from the old old LTS (14.04) to 16.04
<whitequark> oh
<rqou> and (initially) you couldn't even log in anymore
<whitequark> you mean -dist-upgrades
<whitequark> that's a different beast entirely
<rqou> yeah
<rqou> normal upgrades on ubuntu work great
<rqou> the only problem is that their packages become stale AF
<whitequark> why were you doing a dist upgrade in the middle of a semester during crunch time?
<whitequark> this is stupid
<rqou> i wasn't
<rqou> i would defer it
<rqou> i basically jumped ship after i had deferred an upgrade long enough that i couldn't install packages anymore
<rqou> because the old stuff had been purged from the archives
<rqou> but overall i'm not too happy with ubuntu but don't really see a better choice for servers
<rqou> i wonder how much the upgrade to 18.04 will make me angry
<whitequark> awygle: idle thinking
<whitequark> on "next-glasgow" we might want to use SPDIF physical layer for sync port
<whitequark> not sure how much does it actually matter
<rqou> wtf
<rqou> why?
<whitequark> rqou: so that you don't have a common ground
<rqou> aah
<rqou> neat idea
<rqou> the only problem is that i've never actually seen an spdif cable irl
<rqou> make it both? :P
<whitequark> "wtf why" → "neat idea"
<whitequark> toslink cables are extremely cheap
<rqou> "why not a SFP" <-- azonenberg :P
<whitequark> no, that was azonenberg's idea, actually
<whitequark> well it's derived
<rqou> ooh yeah now i remember
<rqou> wait...
<rqou> i thought that was _my_ idea
<rqou> for doing instrumentation for azonenberg's smart PSU/PDU
<whitequark> oh, dunno, maybe
<whitequark> i don't remember
<awygle> I don't think isolated ground is a big deal for sync. More for duts imo
<awygle> Toslink is very cheap though
<whitequark> also it looks like you'll need a dual toslink cable or something
<whitequark> since there are no combined transceivers
* awygle briefly longs for a really good sound system
<whitequark> wtf is mini toslink
<awygle> Isn't that a vendor thing? Aka not standard?
<awygle> God I love marketing copy on high end av cables
<awygle> I'm gonna start a tumblr
<whitequark> seems so
<rqou> whitequark: it's how they squeeze toslink into macbooks
<rqou> which most people don't even know about until they run linux and encounter the bug where linux doesn't seem to be able to turn the toslink LED off
<rqou> because apparently HDA Audio is a massive piece of junk
<whitequark> lol
<whitequark> does differential manchester encoding count as 1b/2b?
<rqou> i guess?
<gruetzkopf> hmm, spdif switching always worked for meTM
<whitequark> gruetzkopf: btw i bought some 600W stew cooker for vapor phase soldering
<whitequark> comes with a nice wire thingy for putting a PCB on
<gruetzkopf> neat
<whitequark> how do I get the heat transfer liquid off the PCB once I'm done?
<gruetzkopf> for me tilting the pcb is enough
<gruetzkopf> maybe shake it once
<gruetzkopf> it really doesn't stick well to PCBs
<whitequark> nice
<whitequark> does it dissolve flux?
<gruetzkopf> not really
<gruetzkopf> takes a while to noticable aquire flux
<whitequark> oh
<whitequark> I can always distill it
<whitequark> just simple distillation
<awygle> do please report on how this goes, it sounds super cool
<whitequark> awygle: oh I can send you some Galden too
<whitequark> I have waaaay too much
<awygle> sure! That'd be cool
* awygle needs a new positive descriptor
<whitequark> "hot" ?
<awygle> I mean the Galden will eventually be hot
<whitequark> lol
<whitequark> huh, there's apparently *vacuum* vapor phase soldering
<gruetzkopf> yeah
<gruetzkopf> for those annoying power packages with 2cm² power pads
<awygle> I can see how that would help but it seems like it would rarely be worth it
<whitequark> apparently it's for void free
<whitequark> awygle: i love how the machine that does it is called "ASSCON VP800" https://www.youtube.com/watch?v=udNd1DygbvU
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<awygle> ASSCON, the premier industry trade show for manufacturers of adult recreational devices
<mithro> Anyone used https://github.com/yaqwsx/PcbDraw ?
<Zorix> that looks neat
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<whitequark> mithro: the libraries are kinda underwhelming
<awygle> assmann does make good cheap connectors
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<rqou> mithro: why not just render the 3d model?
<mithro> rqou: Nice 2d-diagrams are good for doing pin layout and similar
<rqou> can't you render the 3d model in ortho view?
<rqou> also wtf: herp derp what is a semver
<rqou> thanks japaric
<awygle> I accidentally an anime instead of a PCB again... Should have done late dinner lol
<awygle> rqou: what happen
<rqou> the "heapless" crate isn't semver compliant
<rqou> 0.2.4 to 0.2.5 is a breaking change
<awygle> It's pre 1, isn't that allowed?
<rqou> hmm maybe
<rqou> maybe i'm on the wrong nightly version for it
<whitequark> rqou: it is allowed
<awygle> that has to be intentional
<awygle> I refuse to live in a world where that's an accident
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<mithro> IPXS (Image Processing for XS boards) that I developed in the late 90s for the Xess XC4010 boards
<mithro> daveshah: ^^
<openfpga-github> [Glasgow] whitequark pushed 3 new commits to master: https://github.com/whitequark/Glasgow/compare/34a9a3da70dd...a59b11a6cb7f
<openfpga-github> Glasgow/master a59b11a whitequark: Minor I2C cleanup.
<openfpga-github> Glasgow/master 4faa9af whitequark: Fix typo in documentation.
<openfpga-github> Glasgow/master 396f909 whitequark: Set I2C MultiReg reset state back to 1.
<whitequark> awygle: you don't write enough tests ;___;
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<rqou> mithro wtf are you working on right now?
<mithro> rqou: I'm avoiding work by going through my RSS feeds
<awygle> azonenberg: in your oven, do you put the metal trays in?
<azonenberg> awygle: Yes
<awygle> K
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<awygle> azonenberg: how long after melt?
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<azonenberg> awygle: I wait until all visible solder have melted, then turn off heat after 30 sec above liquidus then open the door
<awygle> Mk that's basically what I did (45 sec after first melt, which is close to the same)
<azonenberg> Yeah 30-45 is about right
<awygle> Next time I need to center more carefully front/back
<azonenberg> you had thermal gradients?
<azonenberg> my oven is super uniform, the convection fan helps a lot with this
<awygle> Little bit, not *too* bad but definitely visible
<azonenberg> As far as all solder melting very close to the same time
<awygle> Yeah this one has a fan
<azonenberg> There's usually only a few seconds in which some stuff is melted and others isn't
<awygle> I'm not sure which elements were on though
<azonenberg> the one exception is big SMA connectors
<lain> azonenberg: did you insulate your oven?
<azonenberg> Those take time
<azonenberg> lain: no
<awygle> I set it to toast, not cookies :-P
<azonenberg> it's literally stock
<lain> interesting
<azonenberg> awygle: yeah i looked in the manual
<azonenberg> cookies has all elements on + fan
<azonenberg> (on this oven)
<azonenberg> Which is what i wanted
<lain> we got a big convection oven and bolted a controller on, but measurements indicate we got a large thermal gradient with the fan on
<awygle> I have an independent fan control knob
<lain> turning the fan off resulted in more even heat
<azonenberg> lain: interesting
<lain> reading up online, people said it's a really good idea to insulate and add reflective tape inside
<azonenberg> i got much better results with it on, though i want to fine tune the oven down the road
<lain> interesting
<azonenberg> My plan is to insulate with aluminum foil plus maybe glass wool or something
<azonenberg> Build my own controller, not for profiling per se but i want to be able to push the temp 10-15C hotter to hit the optimal process temp for SAC305
<azonenberg> Then put in a hose barb so I can feed N2 purge gas in
<whitequark> awygle: btw why not vapor phase
<whitequark> no need for N2 purge
<awygle> There's no obvious indication of which elements are on in which mode, but if the bottom ones were on I feel like the top should be?
<azonenberg> and then set up some kind of hood or exhaust system on top
<awygle> There was a surprising amount of fumes though
<azonenberg> To catch the fumes
<awygle> Wonder if that's just because it's new
<azonenberg> Yes, that is typical from all of the flux melting at once
<awygle> whitequark: I had never looked into it until last week
<azonenberg> Thats one of the reasons i wanted both inerting and exhaust in the new lab
<azonenberg> inerting = less combustion of flux
<awygle> azonenberg: yeah but even by that standard this seemed excessive
<azonenberg> exhaust = outgassing is vented outside
<azonenberg> how much? visible smoke comnig off the board?
<whitequark> erm
<awygle> is smol board
<whitequark> azonenberg: why not vapor phase
<whitequark> not awygle
<azonenberg> whitequark: expensive, hard to obtain
<awygle> Visible out of the top of the oven
<azonenberg> in the US
<awygle> Not near the board
<whitequark> azonenberg: hard to obtain?
<azonenberg> whitequark: in small volume, in the us? yes
<whitequark> not at all
<whitequark> sec
<azonenberg> Biggest issue is, i have a convection reflow process dialed in
<azonenberg> it works and i'm confident, i just want to tweak it a little
<awygle> myyy apartment smells bad now
<azonenberg> And while vapor phase seems cool, i don't see the benefits
<azonenberg> for my use case
<awygle> gotta work out a better system for exhaust
<whitequark> oh hm, the supplier i was thinking of doesn't sell the HTF that works for lead-free
<whitequark> so you might be right on that art
<awygle> I overpasted this a bit but it's pretty solid. Just have to zap a couple shorts. Not bad for first board in 2+ years
<awygle> (first board I assembled myself)
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<azonenberg> awygle: glasgow or something else?
<awygle> else
<awygle> This is my LNB board
<awygle> Tomorrow is smolfpga
<awygle> I'll post pictures in a bit, taking cat for a walk
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<awygle> https://twitter.com/awygle/status/990470050921439232?s=19 I really need to learn to take good pictures
<whitequark> awygle: I think you have tombstoning in U5 and U6
<whitequark> L1 also looks sketchy
<awygle> I do, yeah. I overpasted.
<awygle> Nothing irreparable though
<awygle> My favorite is C22
<whitequark> lol
<awygle> I imagine it's waving. "Hi Mom!"
<awygle> Anyway, this is why I did the less critical board first. Fix it up tomorrow, do smolfpga, see Infinity War. Good weekend.
<openfpga-github> [Glasgow] whitequark pushed 1 new commit to master: https://github.com/whitequark/Glasgow/commit/af95c912cdef2e02c181d3663eb98b85cf69069d
<openfpga-github> Glasgow/master af95c91 whitequark: Fix I2C read stobe timing and add more elaborate tests for reads.
<whitequark> awygle: ^
<awygle> whitequark: sorry :-(
<whitequark> no it's fine
<whitequark> just showing what i meant
<whitequark> the read stobe issue was trivial, just needed before_entering vs after_entering
<whitequark> hmmm what should I do now
<awygle> ah, I see
<openfpga-github> [Glasgow] whitequark pushed 1 new commit to master: https://github.com/whitequark/Glasgow/commit/af56fb21f94e7a8e1299c72524e8d45ef38322c1
<openfpga-github> Glasgow/master af56fb2 whitequark: gateware/
<whitequark> hm wtf
<openfpga-github> [Glasgow] whitequark force-pushed master from af56fb2 to 3a62c33: https://github.com/whitequark/Glasgow/commits/master
<openfpga-github> Glasgow/master 3a62c33 whitequark: gateware/ → software/glasgow/gateware/...
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<openfpga-github> [Glasgow] whitequark edited wiki page Parts https://github.com/whitequark/Glasgow/wiki/Parts
<rqou> huh, i just ordered from mouser for the first time (i normally use only digikey) and i'm quite disappointed in their boxes :P
<whitequark> lol
<whitequark> rqou: azonenberg: btw i did not find any solder paste in hk
<rqou> hey, digikey boxes look really nice ok?
<whitequark> possibly because it needs refrigerated storage
<rqou> lolol
<whitequark> annoying
<rqou> btw, SFE still has really really nice boxes
<rqou> (not so much their actual products though)
<rqou> also: azonenberg: any particular reason why a castellated module would be MSL3?
<azonenberg> rqou: no idea, components on it?
<azonenberg> they still get hot and can popcorn
<rqou> but i have a different module here that is MSL1
<azonenberg> Different chips
<azonenberg> i've seen some really strange stuff be MSL1 that i'd expect to be 2-3
<rqou> i guess
<rqou> or maybe espressif just doesn't give a shit :P
<whitequark> is MSL like, actually important
<whitequark> or is it just paranoia
<azonenberg> I generally try to bake high-value components if they've been out for longer than the MSL limit (FPGAs, fancy ADCs, etc)
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<azonenberg> anything worth less than like 10 USD per chip i generally won't worry about in a prototype
<azonenberg> if it actually popcorns i'll just buy another and replace it
<rqou> i never bake "jellybean" standard QFP/QFNs
<rqou> i would probably bake an FPGA
<rqou> or just never open the bag
<whitequark> is an UP5K a jellybean QFN? :P
<azonenberg> yeah whenever possible i just use fresh chips boguht for the project
<rqou> yes
<azonenberg> whitequark: basically my rule for small volume runs is
<rqou> i pretty much use the same heuristic as azonenberg
<azonenberg> think about how upset you'd be if the chip didn't survive
<azonenberg> is a 1% or so chance of that a problem?
<whitequark> that... makes sense
<rqou> whitequark: i just asked my dad and he claims that most people just hop over to SZ to buy solder paste
<azonenberg> Certainly in mass production it would cause unacceptable yield loss
<whitequark> rqou: wtf
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<azonenberg> whitequark: i had a hard time even finding *flux* in apliu st
<rqou> it's only ~1 hr away during off-peak hours you know :P
<whitequark> but visa
<rqou> oops :P
<whitequark> what oops
<whitequark> don't tell me you don't need one
<rqou> i personally do not need one
<whitequark> how come the hk<>cn immigration policy is not reciprocal?
<whitequark> mainland people need a hk visa but hk people don't need a mainland visa?
<rqou> yup
<rqou> you need a "home return permit"
<rqou> also, "it's still one country, just two systems"
<azonenberg> rqou: inb4 taiwan
<rqou> yeah there's another system for that
<rqou> azonenberg: you would need a "Mainland Travel Permit for Taiwan Residents, also known as Taiwan Compatriot Permit"
<whitequark> Taiwan Compatriot
<rqou> yes
<whitequark> wonderful euphemism
<rqou> hey, if the koreas can show signs of sorting out their differences, there's still hope for sorting out this mess too
<openfpga-github> [Glasgow] whitequark pushed 2 new commits to master: https://github.com/whitequark/Glasgow/compare/3a62c336da78...ff0a04ab77c5
<openfpga-github> Glasgow/master ff0a04a whitequark: Use a pads object for I2C instead of separate scl/sda signals....
<openfpga-github> Glasgow/master 0a0e734 whitequark: Assign an I2C address to the FPGA.
<openfpga-github> [Glasgow] whitequark pushed 1 new commit to master: https://github.com/whitequark/Glasgow/commit/bdb39b3ab133dea7bb866505d047425d31a4839f
<openfpga-github> Glasgow/master bdb39b3 whitequark: Move GlasgowDevice to glasgow.device and add __all__ everywhere....
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<whitequark> awygle: oh WTF
<whitequark> Timing estimate: 21.86 ns (45.74 MHz)
<whitequark> Checking 20.83 ns (48.00 MHz) clock constraint: FAILED.
<whitequark> this is just I2C alone
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<rqou> O_o the BMD-300 is so smol and cute
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<rqou> pricey though
<rqou> awygle: wtf your code is teh sux :P
<rqou> awygle: did you take cs150?
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<whitequark> awygle: somewhat better with --no-promote-globals but... i'm afraid we'll have to go to hx
<rqou> did you optimize anything?\
<rqou> my "herp derp whatever" HDL tends to get a bit over 60 MHz on an HX
<whitequark> rqou: it's an extremely simple core
<whitequark> honestly unsure what can be optimized in it
<rqou> hmm
<daveshah> Well, the hard SPI core in the UltraPlus only manages 45MHz
<rqou> just build it for hx and see what you get?
<rqou> daveshah: wtf
<rqou> that's slow as shit
<daveshah> Yeah, but it's like half the static power per LC compared to the iCE40LP parts
<whitequark> who cares about static power in a part that has DSP and SPRAM?!
<daveshah> idk
<daveshah> "smart" gadgets
* whitequark . o O ( can you overvolt Vcore and make it faster )
<daveshah> tinyfpga is going to try that at some point
<daveshah> you could characterise the improvement (or not) fairly easily with a ring oscillator
<whitequark> yeah
<rqou> whitequark: just build for an hx and measure timing?
<daveshah> Personally I'd aim for 24MHz on the UltraPlus
<rqou> wtf
<rqou> that's sloooow
<whitequark> daveshah: welllll
<daveshah> Absolute max Vcore is 1.42V
<daveshah> Plenty of OC/OV room
<whitequark> the interface clock is either 48 or 30 MHz
<whitequark> from the Cypress chip
<daveshah> 30MHz then
<rqou> what process node is this on?
<whitequark> I *could* take it via a PLL and down to 24 MHz
<whitequark> and then use DDR primitives
<whitequark> in principle
<rqou> i was hitting 50 mhz easily on s3
<daveshah> yeah but that has like 3 orders of magnitude more static power
<daveshah> the optimisation target for the ice40 is *not* clock
<daveshah> particularly the ultraplus
<rqou> hmm
<whitequark> who tf called it "ultraplus"
<rqou> it still kinda feels like UP has optimized themselves into a pretty crappy niche
<whitequark> yes
<whitequark> it's dumb
<daveshah> yeah, I agree from my PoV too
<daveshah> but the places these are going into don't care
<daveshah> these are parts for people ordering 10s of millions really
<whitequark> for comparison
<whitequark> I hit 112 MHz on the same design on HX8K
<rqou> O_o
<rqou> nice
<rqou> i guess awygle does know how to HDL :P
<whitequark> I wrote most of that HDL anyway
<rqou> also wtf that means UP is really really slow
<rqou> i guess you're better than me at it
<whitequark> lol
<daveshah> it's way worse than an LP part even
<rqou> my "lol whatever don't care" hdl pretty consistently only hits ~65 MHz on HX
<whitequark> lolol
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<openfpga-github> [Glasgow] whitequark pushed 2 new commits to master: https://github.com/whitequark/Glasgow/compare/bdb39b3ab133...ac2dad6ec263
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<openfpga-github> Glasgow/master ac2dad6 whitequark: Add Glasgow platform, programmer and target.
<openfpga-github> Glasgow/master 0f351cd whitequark: Correctly use TSTriple in I2C gateware.
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* whitequark ponders
<whitequark> awygle: do you have an opinion on the license for Glasgow
<whitequark> I'm tempted to go with my usual 0-clause BSD
<whitequark> rqou: wtf why aren't you sleeping
<rqou> good question
* rqou zzzzzzzzz
<Ultrasauce> sleep is for the weak
<Ultrasauce> you're gonna do a run of those right? maybe I should procure one. been fantasizing about the sort of socratic dialogues with hardware it'll enable
<Ultrasauce> a process currently limited by not wanting to bother writing firmware
<whitequark> Ultrasauce: Glasgow? yeah
<whitequark> socratic dialogue lol
<whitequark> but I'm *definitely* going to first prove that I can pass timings now before making a production run
<Ultrasauce> yeah theres certainly no point if the fpga is too wimpy
<whitequark> I have several features in the design that make it possible to work with even real slow gateware
<whitequark> I thiink down to 6 MHz
<pie_> can i do led pwm with that
<pie_> jk
<whitequark> the FPGA has no leds connected to it
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<openfpga-github> [libfx2] whitequark pushed 1 new commit to master: https://github.com/whitequark/libfx2/commit/f3d0f8e9b3fe8ff87f9bacac363d7f34e676ecdd
<openfpga-github> libfx2/master f3d0f8e whitequark: Expose FX2Device.load_ram and fx2.format.{input_data,output_data}.
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<openfpga-github> [Glasgow] whitequark pushed 2 new commits to master: https://github.com/whitequark/Glasgow/compare/ac2dad6ec263...cef3425f584d
<openfpga-github> Glasgow/master cef3425 whitequark: Automatically load FX2 firmware if it isn't loaded yet.
<openfpga-github> Glasgow/master 30d5d22 whitequark: Add a CLI action for downloading test bitstream.
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<openfpga-github> [Glasgow] whitequark pushed 1 new commit to master: https://github.com/whitequark/Glasgow/commit/1ed8bc4caf718e25619e64846ba884de38ace56d
<openfpga-github> Glasgow/master 1ed8bc4 whitequark: Set production pinout for FPGA configuration.
<whitequark> so
<whitequark> `glasgow test` now uploads the firwmare and builds+uploads bitstream
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<whitequark> that is rqou definitely
<Ultrasauce> i swear i've written more //TODO lines than statements in the last couple hours
<Ultrasauce> we'll call that design
<jn__> now get someone else to work on your TODO items :)
<pie__> //TODO do the TODOS
<pie__> //TODO stop writing TODOs
<Ultrasauce> couple FIXMEs too, naturally
<pie__> //FIXME: write any actual code
<pie__> best spec is an executable spec, amirite
<Ultrasauce> if the vp8 team can do it so can i
<jn__> pie__: TODO("write code")
<jn__> ;
<pie__> ironically that can also be understood as, the spec is the reference implementation, which i get the feeling might be a bad thing
<pie__> make the spec the reference implementation, and not the reference implementation the spec!
* pie__ closes irc because homework
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<awygle> whitequark: not really no (re license)
<awygle> I would not use CC0 but I don't care very much and I consider this your board
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<whitequark> awygle: what would you use?
<awygle> whitequark: in the absence of external forces, probably OHL or CC-BY-SA
<whitequark> awygle: and software?
<awygle> GPL3 for the firmware, gateware same as hardware (but I haven't really dug into appropriate licensing for gateware)
* whitequark looks at OHL
<awygle> That's my biases though. CC0 is the best way to minimize the encumbrance which is my understanding of your preference
<whitequark> "The Licensee [...] he [...] he [...]" ok fuck that noise
* awygle winces
<awygle> Fuck seriously
<awygle> Get it together CERN
<whitequark> I would modify it but "Anyone is welcome to use the CERN OHL, in unmodified form only, for the distribution of his own Open Hardware designs."
<whitequark> >his
<whitequark> lol nope
<awygle> Yeah fuck that. I never noticed that (thanks privilege).
<whitequark> awygle: I don't think I can license gateware same as hardware
<whitequark> it's Python code
<awygle> ahhh yeah
<awygle> didn't think about that
<awygle> like i said i haven't really investigated gateware much
<awygle> i'm perfectly happy to go CC0 for the whole thing
<awygle> or CC0/BSD0 or something
<whitequark> I mean, technically, that's Free, right
<awygle> lmao
<awygle> that's amazing
<Bike> if the document is causeless sense data why would i follow its orders and denounce it as such
<Bike> this will never hold up in court.
<whitequark> hahaha
<whitequark> but why would I care about it holding up in court?
<Bike> good point
<awygle> this is the first one of these "joke" licences i've actually respected
<whitequark> it's srs bzns
<Bike> given that my memories could be falsified as well, i think it's reasonable to say it's the only bzns.
<whitequark> indeed
<felix_> re cern ohl: wat?! o_O i wonder if or when they'll change that; i mean using a singular they/their works quite well in english. in german you can only either use plural or have some construct that makes your eyes hurt. will probably pick another license for my current open source hardware project; thought that i've solved the which license to pick question; didn't really read the license text though
<felix_> tbh...
<cpresser> i just looked up the cern ohl thing. it seems they changed it in version 1.2
<cpresser> "... for the distribution of their own Open Hardware designs."
<whitequark> oh
<whitequark> ope
<whitequark> *nope
<whitequark> wtf is that URL
<whitequark> anyway that still has "he" all over the actual license text, with similar implications
<cpresser> yep, weird that they changed the preamble, but not updated the license
<cpresser> but then again, its the english language which I am not a native speaker of. so i should just shout my mouth.
<whitequark> meh, english is the international language. americans don't have monopoly on deciding what's right in it
<awygle> It was mentioned on the mailing list in 2012 >_<
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<whitequark> there's been like one email to the list in both 2017 and 2016
<awygle> yep
<awygle> That poll is very interesting to me
<awygle> 2:1 ratio
<openfpga-github> [Glasgow] whitequark pushed 3 new commits to master: https://github.com/whitequark/Glasgow/compare/1ed8bc4caf71...47591c4eaac7
<openfpga-github> Glasgow/master 47591c4 whitequark: Add licenses (0BSD and Apache-2.0).
<openfpga-github> Glasgow/master a90cbde whitequark: Update .gitignore.
<openfpga-github> Glasgow/master 81ea988 whitequark: Add the rest of FX2 pinout and LED control code.
<rqou> 0BSD _and_ Apache-2.0?
<whitequark> yes
<rqou> why?
<whitequark> apparently some people care about patent clauses
<awygle> Yeah Apache 2 is definitely the most biz friendly license
<whitequark> I would obviously never take out a patent on anything in it but it also costs me nothing to add Apache-2.0 and it follows the spirit behind using 0BSD
<awygle> whitequark: thanks for, uh... Giving a shit what license I prefer I guess? Lol
<awygle> Unnecessary but appreciated
<whitequark> well, I don't consider myself automatically right, it was worth investigating
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<daveshah> rqou: sorry to pester, but are you still planning to do those ice40 die photos?
<rqou> yes
<rqou> i _might_ get to them this week
<rqou> but if not you'll probably have to wait for two weeks
<rqou> upcoming week is dead week (no classes)
<rqou> but week after that is final exams
<whitequark> awygle: actually I don't care about businesses
<whitequark> if they're scared of patents that's their problem, not mine
<whitequark> I do care about academia though, and I was told Apache also makes things easier there "somehow"
<balrog> > I was told Apache also makes things easier there "somehow"
<balrog> offices of university counsel tend to be irksome, sometimes
<balrog> afraid of any liability
<whitequark> yeah that's a reason good enough
<daveshah> rqou: sure, no worries
<daveshah> just want to see them at some point :)
<awygle> That makes sense to me yeah
<mithro> whitequark: Normally it's the patent stuff which makes Apache 2.0 considered better
<whitequark> yep
<whitequark> that's why
* whitequark stares at code
<whitequark> so I'm using the same code paths to access EEPROMs and FPGA registers because the Cypress chip doesn't have a lot of code RAM
<whitequark> I feel gross
<mithro> whitequark: Yeah - the FX2 frequently makes you feel gross :-(
<jn__> 8051 :|
<awygle> I constantly mock my father for the extremely dicklike shape of the rocket he works on, glad to see Twitter agrees
<rqou> your father works for spacex?
<awygle> Blue Origin
<awygle> Google New Shepard if you haven't seen it
<mithro> hey awygle - Any chance you'll get time to review those schematics today?
<awygle> mithro: this evening yeah
<mithro> awygle: Hust to be clear, I'm after review to make sure the PCB can be routed. I'm definitely expect there to be issues like missing junction dots, unconnected nets, etc.
<mithro> awygle: I also haven't done a DRC check or anything myself
<awygle> mithro: so more a feasiblility check than a detailed design review?
<azonenberg> mithro: have you done ERC?
<whitequark> grumble grumble kicad ERC is next to useless
<mithro> awygle / azonenberg: the schematic was done by a person who is not a schematic designer
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<mithro> So it should mostly "look right" but probably has issues like I mentioned above
* whitequark is reminded of that Lattice FPGA devboard
<asy> awygle: there is no shame to work on flying penis.
<whitequark> blue origin should release company branded dildos as promo
<whitequark> untapped market
<whitequark> now the silicon valley libertarians could *literally* suck bezos' dick
<rqou> lol
<whitequark> after that elon musk couch thing i'm sure someone will do it, live, on youtube
<whitequark> cheered on by hacker news
<whitequark> there is not enough alcohol in the world to erase that mental image
<felix_> mithro: hm, i wonder why do you want to make a new board with a spartan 6 on it?
<mithro> felix_: in the repo?
<felix_> yep
<felix_> only looked at the description, not the schematics though
<felix_> or are you planning to looking into continuing the work on the s6 fpgatools? ;)
<mithro> felix_: Because the s6 is currently *super cheap* in China
<mithro> felix_: We will see if I ever actually make the board, it's the lowest priority
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<felix_> ah, ok. do those cheap s6 still work properly? i'm a bit sceptical about salvaged chips
<balrog> isn't the s6 pretty hated? :P
<mithro> felix_: Seem too
<mithro> I'm willing to risk it if I can get the boards in the $10 USD range...
<daveshah> this using luke's bootloader?
<felix_> oh, a board in the 10$ range with an fpga that isn't tiny would indeed be nice
<daveshah> it would totally change perceptions about FPGAs
<daveshah> obviously a board in the 10$ range with a big FPGA and open tools would be even better
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<pie__> whitequark, i dont know what this is but https://twitter.com/kauza_a/status/989162222873075714
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<awygle> OH: "I wonder who got the wind tunnel model"