<qu1j0t3>
maybe there should be a warning or something.
pie_ has quit [Ping timeout: 240 seconds]
<rqou>
linux? warnings? don't be ridiculous :P
<qu1j0t3>
:(
wdfwefewvfgew has joined ##openfpga
wdfwefewvfgew has left ##openfpga [##openfpga]
<rqou>
offtopic: anybody here familiar with the epitome of usability, gpg?
<rqou>
azonenberg?
<jn__>
what do you want to do with gpg?
<rqou>
i finally got around to signing keys from the extremely-poorly-organized 33c3 keysigning party
<rqou>
now i need to do the "email sending" part
<rqou>
but my key is on an offline system
<rqou>
so i've already manually done the "download keys" and "check fingerprint" steps
<rqou>
how to i automatically do the "split by uid" and "send email" steps?
<rqou>
alright, so apparently caff can still do it as long as you import all of the keys into its keyring
<rqou>
alright, now for a dumb unix question
<rqou>
suppose i have a batch of raw emails in files, how do i feed them to the interwebs?
<rqou>
i have a working local mta
<rqou>
alright, apparently "sendmail -t" will ingest mail files
<rqou>
so how many iterations of "why johnny can't encrypt" are we on at this point? :P
m_w has quit [Ping timeout: 240 seconds]
<cr1901_modern>
I use GPG for passwords, that's about it. I wish Signal wasn't the de facto standard b/c it's lock-in (and the author has no interest in financially supporting alternatives)
m_w has joined ##openfpga
<azonenberg>
rqou: fwiw i use GPG but i dont do key signing or WoT
<azonenberg>
i manually verify keys for the people i talk to
<azonenberg>
out of band
<rqou>
that seems even more work
DocScrutinizer05 has quit [Disconnected by services]
DocScrutinizer05 has joined ##openfpga
mifune has joined ##openfpga
mifune has joined ##openfpga
mifune has quit [Ping timeout: 260 seconds]
<azonenberg>
whitequark (and others): I have a project where i really want to have a constraint file format for greenpak
<azonenberg>
Any thoughts on what the file should look like? is there some kinda standard to be used?
<cr1901_modern>
I
<cr1901_modern>
'm partial to what arachne-pnr accepts :P
<azonenberg>
Got a link to a spec or anything?
<azonenberg>
i will be making an arachne back end for splash at some point
<azonenberg>
So being able to generate more constraint files with less code would be ideal
<cr1901_modern>
set_io [net_name] [pin_name]
<cr1901_modern>
that's it.
<azonenberg>
what about io standards/voltage levels etc?
<azonenberg>
not that gp4par needs that right now
<cr1901_modern>
It's not supported :D!
<azonenberg>
as of now my list of constraint formats to support are xilinx UCF, xilinx XDC, whatever arachne does, whatever gp4par does, whatever my coolrunner tools will do
<azonenberg>
And only UCF is implemented
<cr1901_modern>
I looked into adding it, but I lost interest, tbh
<azonenberg>
well for coolrunner voltage spec is mandatory
<azonenberg>
there's a bit that has to be set to config the io drivers or the chip fries
<azonenberg>
(or the inputs just act really weird, depending on which way its wrong)
<cr1901_modern>
The solution for icestorm is to manually instantiate pins and set the parameters you want (such as pullup and i/o standard)
<cr1901_modern>
Oh and sweet fucking Jesus atom is taking forever to load a text file w/ an example Arachne PCF
<azonenberg>
and so the thing is
<azonenberg>
in splash i am trying to be generic
<azonenberg>
and allow compiling a design for multiple boards
<azonenberg>
which may have totally incompatible pinouts and io standards
<azonenberg>
the rtl has to not make any assumptions about the boards
<azonenberg>
basically you specify the hdl and a list of board files
<azonenberg>
(which are technology independent)
<cr1901_modern>
I'm going to be kind and *not* link that goddamn xkcd comic. But I like arachne's simple command src dest format best
<azonenberg>
Yeah i may use that for my tools
<azonenberg>
but i'll add additional extensions to that
<azonenberg>
say set_voltage [net] [level]
<azonenberg>
or something
<cr1901_modern>
perhaps put your changes back into arachne as well... I mean your tolerance for C++ is higher than mine
<azonenberg>
eventually, i want splash to be able to compile the same hdl for a greenpak with my tool, a spartan6 with ISE, a coolrunner with my tool, a 7 series part with vivado, and an altera part with quartus
<azonenberg>
(assumign it fits in all the chips)
<azonenberg>
with different pinouts and voltage levels
<azonenberg>
just by specifying a list of boards to target
<azonenberg>
i will definitely be messing with arachne (and icestorm in general) down the road
<azonenberg>
but right now i dont have a huge need for midrange fpgas
<azonenberg>
i either need huge (7 series) or tiny boot/reset type parts (greenpak)
<cr1901_modern>
azonenberg, in my experience, if you want an HDL design to be generic, a specific set of I/O pins are in general going to use the same voltage level between vendors
<azonenberg>
i mean one board might have 3.3v i2c and another might have 1.8
<cr1901_modern>
you may wish to look into how Migen does it
<azonenberg>
with the same parts hanging off them (or well, protocol compatible at least)
<azonenberg>
even just a respin of one board for the simple case
<cr1901_modern>
Migen has a platform.request("i2c") for each board it supports
<azonenberg>
where a pin changed banks
<cr1901_modern>
it's up to the board description to specify the correct I/O voltage and slew etc
<azonenberg>
Thats what i do here
<azonenberg>
the point is, i need to have a constraint file for that to work
<azonenberg>
since i have one hdl file and multiple constraints
<azonenberg>
i dont generate hdl per board
<cr1901_modern>
(Well, you might have to have hdl per board in some cases if you use primitives)
<cr1901_modern>
or at the very least per-vendor
<cr1901_modern>
Again, I suggest looking at how migen does this
<azonenberg>
Except i dont use primitives
<azonenberg>
i use a ReconfigurablePLL or ClockBuffer or DDROutputBuffer etc
<azonenberg>
And that does `ifdef XILINX_7SERIES foobar
<azonenberg>
`ifdef LATTICE_ICE40 blah
<azonenberg>
etc
<azonenberg>
i still synth per board but the source is the same
<cr1901_modern>
I mean, that's fine too
<azonenberg>
the point is, gp4par currently requires (* LOC = foobar *) per top level port
<azonenberg>
there's no other way to do it
<azonenberg>
so my options are to either update splash to patch the source per board
<azonenberg>
or to update gp4par to take constraint files as an alternate input format
<azonenberg>
i prefer that
<cr1901_modern>
Extending arachne's ucf format and *also* sending your changes back to arachne is prob your best bet imho
<azonenberg>
well short term i am only targeting greenpak
<azonenberg>
so i'll use a similar but not identical format
<azonenberg>
patching arachne to support the same format is later on the todo
mifune has joined ##openfpga
mifune has joined ##openfpga
<whitequark>
azonenberg: I have no real opinion on the format
mifune has quit [Quit: Leaving]
<whitequark>
I think json may not be a bad choice as it's easily parseable by 3rd party tooling
<whitequark>
whereas for arachne-pnr... even *arachne-pnr*s own parser had blatant issues
<whitequark>
e.g. only accepting comments on their own lines, or something stupid like that
<azonenberg>
a lot of languages do that
<azonenberg>
its fine as long as it's doc'd as such
<whitequark>
the thing I'm more concerned about is every tool growing its own, slightly different subset of grammar it recognizes
<azonenberg>
That is a concern, yes
<rqou>
does anybody know how to make <whatever DE Tails is using> not pop up some weird options every time the mouse accidentally moves into the corner?
<cr1901_modern>
JSON has no comments. There are legit reasons to put comments in a PCF file
<azonenberg>
Yes
<azonenberg>
i'm leaning toward arachne's format just because it's simple to generate and parse
<cr1901_modern>
"the thing I'm more concerned about is every tool growing its own, slightly different subset of grammar it recognizes" What tools besides openfpga and arachne?
<cr1901_modern>
This was a while back, but I remember *somebody* discussing in chat for their FPGA RE'ing that they planned to use openfpga for their PAR stuff. The bonus of using arachne's format is that there really isn't any incompatibility if future RE projects decide to target openfpga
<cr1901_modern>
and just have arachne be "it's own thing"
<whitequark>
cr1901_modern: right, kinda missed that detail :p
<whitequark>
scratch json then
<whitequark>
json-with-comments isnt anywhere as much of a legit format
<cr1901_modern>
The fact that json doesn't have comments has made me not-a-fan over the years.
<whitequark>
it's quite fine for its intended purpose, a data interchange format
<whitequark>
but as a configuration format it's pretty bad
<cr1901_modern>
which is how I normally end up using it :P
<azonenberg>
cr1901_modern: this is why i switched to YAML for human-authored files
<whitequark>
yaml has its own massive warts
<azonenberg>
Yes, it does
<whitequark>
but I'd be mostly fine with it tbh
<azonenberg>
i honestly wonder if it's overkill for a constraint entry format though
<azonenberg>
(Other point in json's favor, i have a json parser as a dependency already for gp4par)
* cr1901_modern
gets some paint out for the bikeshed
<cr1901_modern>
I will stick with "I prefer arachne's approach, despite it being limited in its current form" :)
<azonenberg>
What file extension does arachne use for constraints? is there a recommended name?
<cr1901_modern>
I've seen .pcf used on the examples
<azonenberg>
Does arachne support LOC constraints or something?
<azonenberg>
in the HDL?
<cr1901_modern>
I don't know.
flaviusb has quit [Ping timeout: 255 seconds]
<azonenberg>
ok sooo
<azonenberg>
arachne's format by itself can't be used because it has no way to do other constraints
<azonenberg>
What i think i'll do is extend it
<azonenberg>
so i can do for example set_iostandard foobar LVCMOS33
<azonenberg>
etc
<azonenberg>
the general format will be set_[attribute name] [net name] [value] and it'll be added to the netlist just like if it was a verilog attribute
<cr1901_modern>
Works for me!
<azonenberg>
not sure if i'll do set_io verbatim
<azonenberg>
because you'll have to rewrite constraint files between boards anyway for obvious reasons
<azonenberg>
And my constraint is called LOC, a la Xilinx
<cr1901_modern>
I'm not sure what you're saying
<azonenberg>
set_io foo 4
<azonenberg>
would be translated to
<azonenberg>
(* IO = "4" *)
<azonenberg>
[declaration of foo as usual]
<azonenberg>
in the parser
<azonenberg>
Problem is, gp4par takes (* LOC = "P4" *)
<azonenberg>
So i'd need to add a remapping for the IO constraint to turn into a LOC constraint
<azonenberg>
And i'm saying, i'm not sure if that makes sense
<cr1901_modern>
why can't it be an alias (for compatibility)?
<azonenberg>
I certainly could do that
<azonenberg>
And i'm considering it
<azonenberg>
i'm just wondering if there's any point since you have to rewrite the constraint anyway
<cr1901_modern>
and also the "4" is IceStorm specific
<azonenberg>
lattice takes P4?
<cr1901_modern>
ahh no. I just mean if arachne-pnr supported Xilinx, it would prob do "P4"
<azonenberg>
i kept the P prefix for xilinx compatibility because i expected openfpga to target coolrunners eventually
<azonenberg>
OH
<azonenberg>
oh*
<azonenberg>
Well in that case
<cr1901_modern>
for compatibility w/ Xilinx terminology
<azonenberg>
I can add a remapping of set_io to set_loc
<azonenberg>
Which would make my grammar a strict superset of arachne's
<cr1901_modern>
Lattice ice40 does in fact number pins starting from 1
<cr1901_modern>
whereas Xilinx uses the "P" prefix
<azonenberg>
i assume both do BGA coordinates as just A3?
<cr1901_modern>
Idk actually
<cr1901_modern>
I've never actually found the Lattice document for package layout
flaviusb has joined ##openfpga
<azonenberg>
And does icestorm have comments in PCF files?
<azonenberg>
if so how are they denoted?
<azonenberg>
Looks like # to end of line
<azonenberg>
Easy enough
<cr1901_modern>
I couldn't set up my environment fast enough to test
<azonenberg>
then i'll add a remapper to support set_io and translate that to set_loc
<cr1901_modern>
Looks good to me. Unsure whether arachne supports comments on the same line after the constraint
<cr1901_modern>
But I like the idea of the formats being compatible.
<cr1901_modern>
(Up to and not including vendor differences)
<azonenberg>
Yeah
<azonenberg>
My longer term plan was, and continues to be, to use the core openfpga code for my coolrunner toolchain once i fix it up
<azonenberg>
Coolrunner still has its uses, it's way faster than greenpak for starters
<azonenberg>
and its reprogrammable
<azonenberg>
and may have higher logic density depending on how amenable your design is to hard IP
<cr1901_modern>
I'm not interested in a non-5V-tolerant CPLD, tbh
<azonenberg>
Lol
<azonenberg>
Well, for 95% of my applications 5V tolerance is a non-issue
<azonenberg>
But my point is more, i expect to use a lot of the same back-end code
<cr1901_modern>
hey, works for all of us then :). My suggestion would still be to use vendor-appropriate terminology
<azonenberg>
Yeah
<azonenberg>
What i meant is, the constraint parser
<azonenberg>
netlist parser
<azonenberg>
etc
<cr1901_modern>
i.e. LVCMOS33 is a Xilinx term
<azonenberg>
actually, i dont think it is
<cr1901_modern>
Oh, well better for all of us then
<azonenberg>
ok let me rephrase
<azonenberg>
LVCMOS is a JEDEC standard
<azonenberg>
It specifies thresholds for various logic levels
<azonenberg>
LVCMOS33 referring to 3.3V LVCMOS may be xilinx specific
<azonenberg>
When possible i do intend to use attribute names/values that match the vendor tool for compatibility
<cr1901_modern>
My main point was that I don't expect vendor "reserved words" to be the same between vendors, but my suggestion would be...
<azonenberg>
ah yeah makes sense
<cr1901_modern>
yea you just finished my sentence
<azonenberg>
i'm making up my own where needed, aka with greenpak
<azonenberg>
where there was no vendor tool to do it
<cr1901_modern>
Right, and that's fair
<azonenberg>
And in such cases i generally lean toward the xilinx keywords as i am most comfortable with them
<cr1901_modern>
I just don't wanted that goddamned xkcd comic to apply
<azonenberg>
Yeah agreed
<azonenberg>
If there is a standard that works i want to use it
<azonenberg>
The problem is that when you're writing a generic tool
<azonenberg>
you have to work with all of the standards, you dont get to choose :p
<azonenberg>
splash has to generate all of them, openfpga has to parse whatever the chip i'm targeting normally uses
<azonenberg>
etc
<cr1901_modern>
the point being, nobody wants the burden of learning another new standard, for better or worse
* cyrozap
only read some of the scrollback
<cr1901_modern>
(and the reason that comic pisses me off personally is that having to learn competing standards *is* a cognitive burden, and an all-in-one would be better overall but will never take off)
<azonenberg>
yes, agreed
<azonenberg>
synopsys SDC seems to be turning into a de facto standard for high end fpga stuff
<cyrozap>
Not sure if you're all aware, but the PCF files that the Lattice toolchain (and now IceStorm) use is also used by the PSoC tools.
<azonenberg>
cyrozap: is there a doc for that file format?
<azonenberg>
or even some examples of it?
<cyrozap>
azonenberg: It's just SDC
<azonenberg>
Ok, so it is SDC based
<azonenberg>
my understanding is that under the hood sdc is tcl
<azonenberg>
just a restricted subset
<cyrozap>
Probably
<cr1901_modern>
what does arachne use then? sdc?
<azonenberg>
probably a subset of sdc
<cr1901_modern>
it never struck me to think of them as tcl commands
<azonenberg>
let me update docs to reflect that
<azonenberg>
Hmmm
<azonenberg>
so it looks like icestorm set_io is not strictly compatible with the true intent of the lattice set_io command
<azonenberg>
Which also doesnt quite match normal sdc
<azonenberg>
great :p
digshadow has quit [Remote host closed the connection]
<azonenberg>
If i wanted to do true SDC i'd have something more like
<azonenberg>
across the full voltage range and in an environment chamber of some sort at a couple of temps
<nats`>
azonenberg I can help for that I already have a mini setup for thermal test :D
<nats`>
a wood chamber with heater and peltier cooler
<nats`>
managed to do -15 to + 115 inside :D
<azonenberg>
Nice
<azonenberg>
Well, in that case
<nats`>
but how do you infer setup time ?
<azonenberg>
we're going to have to set up some known delays, say pin to pin through the routing matrix
<azonenberg>
then send clock and data phase shifted
<azonenberg>
measure how close you can get before the output goes metastable or is wrong
<azonenberg>
then add some percentage safety margin on top of that
<azonenberg>
(after subtracting the known routing delay)
<nats`>
it has a problem
<azonenberg>
i think it can be done
<azonenberg>
try a couple of chips from different batches
<azonenberg>
across temp and voltage extremes
<nats`>
if we don't know setup time of each different element inside we can't be sure if it's FF setup time or other block
<azonenberg>
i'm talking about if we generate a clock and data, feed to one FF
<azonenberg>
then drive the FF out a pin
<azonenberg>
we can measure the routing matrix delay independently of the FF
<nats`>
but the IOBlock ?
<azonenberg>
and the IOB has no state
<nats`>
could it be the source of the problem
<azonenberg>
its combinatorial
<nats`>
ok
<azonenberg>
We can measure io to io routing delay separately
<azonenberg>
there will be some messy math involved
<azonenberg>
but it can be done
<azonenberg>
My plan is to finish support for the last few hard IP blocks, i've been putting that off
<azonenberg>
basically the adc, dac, and spi need some work
digshadow has joined ##openfpga
<nats`>
and we need to have a jitterless clock/data
<azonenberg>
And then timing analysis is next on the todo
<azonenberg>
You dont need jitterless, you just need a couple of averages :p
<nats`>
I can get one
<nats`>
it's easier with a really low jitter
<azonenberg>
Yes it does
<azonenberg>
it is*
<azonenberg>
also, i don't need to know the exact setup time
<nats`>
I have some femtocell VCTCXO
<azonenberg>
I need to know "the setup time is no more than X"
<azonenberg>
it's OK if i make conservative estimates
<nats`>
is there a way to get the good greenpak board to test that ?
<azonenberg>
Sooo
<nats`>
I'll restart my mini chamber this evening to test :)
<azonenberg>
the premade greenpak board isnt exactly well suited to this, i agree
<azonenberg>
My thought is that we could wait till the tssop greenpaks come out then solder one down to a pcb
<cr1901_modern>
is the idea to make a delay-locked looped for the clock and input stimulus, feed both to an input flip-flop, and decrease the delay until metastability is seen on the output?
<azonenberg>
i can restart my old characterization board project
<azonenberg>
cr1901_modern: basically yeah
<nats`>
cr1901_modern using a si5338 culd do the trick :)
<azonenberg>
io buffer delay shouldnt matter all that much in that case as long as it's consistent
<azonenberg>
you can also swap two pins
<azonenberg>
say use p3 and p4, then p4 and p3
<cyrozap>
azonenberg: The PSoC toolchain has an entire TCL-based SDC library from Synopsis (copyright 2005 :P) that supports up to version 1.7 of the standard
* cr1901_modern
doesn't have a si5338
<azonenberg>
and the delta is your io delay which can be canceled out
<cr1901_modern>
I do have a bunch of Xilinx DCMs though :P
<cr1901_modern>
and PLLs*
<nats`>
uggghh
<nats`>
not dcm
<nats`>
pll at least
<nats`>
DCM are really messy
* cr1901_modern
wouldn't know. They work fine for my purposes
<cr1901_modern>
And greenpak is getting tssop versions?!
<azonenberg>
slg46620 has a tssop version in the latest datasheet
<azonenberg>
no word on ETA
<cyrozap>
azonenberg: So if we _really_ wanted to follow the "standard", we'd have to reimplement all of that, and they have a separate file for each version :/
<azonenberg>
but it'd be easy to make a board for
<azonenberg>
cyrozap: lol yeah i dont plan to do that
<azonenberg>
nats`: i was thinking more like an i2c programmable PLL
Bike has quit [Quit: leaving]
<nats`>
si5338
<nats`>
:D
<azonenberg>
Say the LMK04806
<nats`>
si5338 !
<nats`>
:D
<nats`>
look at it :D
<azonenberg>
Does that have per pin analog delay lines?
<cr1901_modern>
si5338 really does fit the bill there
<azonenberg>
or phase shift?
<cr1901_modern>
but Idk if it can be used as a delay-locked loop
<nats`>
yep
<cr1901_modern>
which is what you really want
<azonenberg>
<20ps phase shift
<azonenberg>
the TI part i mentioned was 25
<azonenberg>
perfect
<cyrozap>
azonenberg: I don't understand why so many companies like to make turing-complete configuration file formats...
<azonenberg>
cyrozap: me neither
<nats`>
cyrozap because they can !
<nats`>
:D
<cr1901_modern>
even a context sensitive config file format is bad
<cr1901_modern>
(ASN.1)
<azonenberg>
lol eew
<azonenberg>
nats`: anyway basically what it comes down to is
<azonenberg>
silego has given me the docs they had
<azonenberg>
there is no published timing data beyond what's in the datasheet
<azonenberg>
Which is insufficient to write a static timing analyzer
<azonenberg>
So we're going to have to characterize the parts ourselves
<nats`>
I agree
<nats`>
at the moment I don't have any silego board
<azonenberg>
This tool is already significantly superior to what they have (as long as you arent using any of the IP I haven't supported, lol)
<cr1901_modern>
I keep meaning to buy the programmer
<cr1901_modern>
it's $50 but comes with a bunch of free samples
<azonenberg>
nats`: So one of the easiest options, now that i think about it
<nats`>
lain get your fucking circadian cycle inline :p
<lain>
lol
<lain>
I have been sleeping longer than usual lately, which is weird
<lain>
think it's cause the weather keeps changing
<lain>
one day it's 50F
<lain>
next it's 9F
<lain>
back and forth
<nats`>
°C ? :D
<lain>
we had like three days in a row where first day was thunderstorm and rain, second day was snow and ice, third was rain again
<lain>
nats`: 10C and -12C for 50F and 9F, respectively :P
<nats`>
:D
* whitequark
yawns
<whitequark>
what's a circadian cycle
<nats`>
it's a palce where circus people do fun stuff :p
<nats`>
place
<lain>
lol
<lain>
I'm normally on a 25 hour day, it works for me :P
<whitequark>
I consider being bound to sunlight underneath me
<lain>
haha
<whitequark>
statistically this is likely to result in a 10-25 year life expectancy decrease
<whitequark>
so I should probably stop at some point
<whitequark>
BUT NOT NOW
<nats`>
:D
<lain>
honestly I would like to be awake during daytime more often because I enjoy the sunlight, and the fast food choices...
<lain>
but it's not my natural state
<whitequark>
my sleep/wake cycle would be less fucked if certain things happened less often
<whitequark>
like more or less accidentally discovering that [REDACTED]ine makes a powerful but shitty stimulant
<lain>
lool
<whitequark>
I can't believe it used to be sold OTC without so much as a sternly worded warning, around the entire west
<lain>
other than caffeine in the morning, I don't take any stimulants. I don't even have much sugar in my diet anymore
<whitequark>
I utterly resent caffeine
<lain>
it doesn't seem to do anything for me
<lain>
whitequark: why? :o
<whitequark>
it sends me into a low-grade tachycardia, which isn't threatening in any way, just incredibly unpleasant, and doesn't really enhance wakefulness so much as induce insomnia
<lain>
ah
<lain>
it's never really had an effect on me
<lain>
aside from that one time when I made the mistake of taking a /lot/ of caffeine
<lain>
like a not-insignificant fraction of the LD50
<whitequark>
what
<lain>
mistakes were made
<whitequark>
okay
<whitequark>
not judging
<lain>
young and stupid, etc
<whitequark>
... trying really hard to not judge, fine
<lain>
haha
<whitequark>
did you do an extraction and wonder what to do with the result
<lain>
nope, just an energy drink and a whole lot of youthful stupidity
<lain>
well, a large case of energy drinks
<whitequark>
was it "five hour energy" by any chance
<lain>
nope
<whitequark>
dang
<lain>
though I have taken that once or twice when I had late nights at work, back during one of my "normal jobs"
<lain>
it keeps me up, but it has some weird effects
<lain>
rofl
<nats`>
<whitequark> it sends me into a low-grade tachycardia, which isn't threatening in any way, just incredibly unpleasant, and doesn't really enhance wakefulness so much as induce insomnia
<lain>
aside from the occasional bit where I stick to a schedule or stay up crazy late, it pretty steadily moves forward on a 25 hour day :P
<whitequark>
huh neat
<whitequark>
whats the device used to acquire this
<lain>
at the moment just my phone, using the "Sleep as Android" app, but it can do actigraphs with my pebble smartwatch
<lain>
I don't typically wear the pebble to sleep though, so it just logs using the phone's accelerometer data, placed near me on the bed
<whitequark>
hmm sounds unreliable
<lain>
in a recent update the app added an ultrasonic thing which is interesting, it will send out inaudible chirps and check for motion on the echo lol
<lain>
I haven't tried that though
<whitequark>
sounds annoying for pets
<lain>
the actigraphs are surprisingly reliable but only for a general restless vs. restful sleep metric
<whitequark>
... I just realized that your dog may actually freak out if you have one of those "APTs" that supposedly communicate via ultrasonics
<lain>
haha
<whitequark>
this is some magic realism shit
<lain>
digital guard dog
ZipCPU_ has joined ##openfpga
ZipCPU|Laptop_ has joined ##openfpga
ZipCPU has quit [Ping timeout: 240 seconds]
ZipCPU_ is now known as ZipCPU
ZipCPU|Laptop has quit [Ping timeout: 258 seconds]
<rqou>
blargh, working on redoing all of the apartment's networking subnets
<rqou>
this sucks
<lain>
subnetting is always a pain
<lain>
I redid my vlans/subnets a while back and blehhhh
<rqou>
there's a huge clusterfuck here of subnets and vlans and NAT
<lain>
I look forward to ipv6
<lain>
everywhere
<rqou>
there isn't even working ipv6 here
<rqou>
i'm working on removing all of the need for stupid double nat-ing
<rqou>
and the "no ipv6" isn't even comcast's fault
<rqou>
it's meraki's
<rqou>
hmm, how "proper" are /112s in ipv6?
<lain>
uhh
<lain>
no idea
<lain>
I have ipv6 through tunnelbroker but it adds latency so I don't use it anymore
<rqou>
i think i can get native dual stack working
<rqou>
but it involves the meraki stack doing dhcp+dns+nat for ipv4
<rqou>
and a different box doing dhcp+dns for ipv6
<rqou>
which is technically totally fine
<rqou>
but idk how tested that is
<rqou>
e.g. stuff like nonauthoritative dns, dns and dhcp not on the same machine, etc
<lain>
I would love to go ipv6-only internally and then only port forward to ipv4 at the router
<lain>
but
<lain>
ok
<rqou>
nat64?
<lain>
the datacenter has ipv6, they have the capability
<rqou>
iirc it exists
<lain>
yeah I can do it but I'm waiting until I have native ipv6 at the DC
<lain>
which.. they do, but nobody has set it up yet
<lain>
and if *I* set it up
<lain>
then I'll own it
<lain>
and I don't need that problem
<lain>
:P
<rqou>
wait, do you work for them?
<lain>
no, but I'm close friends with several people who do, and we exchange favors :P
<lain>
if I setup ipv6 though, they'd come to me any time something went wrong with it
<rqou>
hmm, i need to make friends with the people over at he.net
<lain>
it's a weird informal situation :P
<lain>
he.net is nice
<rqou>
:P
<lain>
that's who my ipv6 tunnel is through, and most of my dns
<rqou>
he.net is basically right next to my parents' house and 30 minutes away from my apartment
<lain>
ohh nice
<rqou>
(not including silicon valley congestion :P )
<lain>
haha
<rqou>
SV congestion turns a ~45 minute drive (berkeley to mountain view) into ~2 hrs
<lain>
hope you like podcasts
<rqou>
it's honestly ridiculous
<rqou>
huh he.net is right next to the tesla factory
<lain>
hm
<lain>
this week I'll probably be working out of the DC again
<lain>
might investigate how hard it'd be to sneak ipv6 into my switch port without affecting the others
<lain>
I dunno how it's setup right now
<lain>
:P
<rqou>
my apartment is currently "hurr durr all on one subnet" :P
<rqou>
um, dumb question
<rqou>
does windows support 802.1q for QoS?
<rqou>
i know it doesn't like vlans natively
<lain>
hm? windows is fine with vlans
<rqou>
really?
<lain>
I've never had an issue, yeah
<rqou>
are you sure it's not the intel enterprise driver making it work?
<rqou>
when i was at broadcom on my work laptop the intel enterprise drivers were just silently eating the .1q tag
<lain>
hm I dunno, I'm mostly doing vlans on my win server box, or with hyper-v
<rqou>
i don't even know how to do qos on my equipment consistently
qu1j0t3 has joined ##openfpga
<rqou>
wtf
<rqou>
apparently meraki can't do ipv6 passthrough and ipv4 nat
<rqou>
meraki mx is the worst device
pie_ has joined ##openfpga
<lain>
:O
<lain>
apparently the DC is indeed handing out ipv6 now, but it's by request only
<lain>
I shall put in a request with joe on tuesday :3
<lain>
wonder if they'll allocate me a /48 haha
<lain>
they might :3
<rqou>
and i have to pull teeth with linode to get 2x /64s
* rqou
is jelly :P
<lain>
he.net gives out /64's, or /48 on request
<lain>
through tunnelbroker.net
<lain>
but I think to get a /48 you have to pass the Sage level competency
<lain>
which also gets you a free t-shirt :D
<rqou>
afaik i can get a /62 once i bypass this stupid meraki mx box
<lain>
(Sage level competency also unlocks IRC usage, cause otherwise people use it for botnets)
<rqou>
it's funny how $FANCY_SCHOOL is super behind on ipv6 deployment
<rqou>
but they used to be a major internet node back in the day
<rqou>
although afaik $FANCIER_SCHOOL (that has a /8) is even more behind :P
<rqou>
$RIVAL_SCHOOL_ACROSS_THE_BAY actually downgraded their /8 a few years back
pie_ has quit [Ping timeout: 240 seconds]
<rqou>
dumb linux question: how do i change from poetteringware ethernet device names to the old "based on mac address" ones?
<rqou>
"There is a lot of misleading information about how to change network names in recent versions of Ubuntu. Some information points to systemd.link, which is just wrong because Ubuntu (as of 16.04) does not use this part of systemd."
<rqou>
so i don't inherently hate poetteringware, but can people please stop doing this ^ shit?
azonenberg_work has quit [Ping timeout: 240 seconds]
pie_ has joined ##openfpga
pie_ has quit [Quit: Leaving]
pie_ has joined ##openfpga
pie_ has quit [Changing host]
pie_ has joined ##openfpga
scrts has quit [Ping timeout: 256 seconds]
scrts has joined ##openfpga
Patater has joined ##openfpga
promach has quit [Ping timeout: 255 seconds]
pie__ has joined ##openfpga
pie_ has quit [Ping timeout: 240 seconds]
pie__ has quit [Ping timeout: 252 seconds]
amclain has joined ##openfpga
pie_ has joined ##openfpga
Bike has joined ##openfpga
eduardo__ has joined ##openfpga
eduardo_ has quit [Ping timeout: 240 seconds]
<pie_>
azonenberg, that fpga cluster you were workin gon at some point makes me think of amazons fpga nodes initiative thing
<pie_>
on that note, i havent looked into that since the announcement came out, anything new with that?
<rqou>
alright, something is definitely f*cked in the apartment wiring
<rqou>
touching the meraki mx is tripping the gfci
<rqou>
(brushed Al body)
<pie_>
rqou, starting to figure out why the modem kills your breaker? xD
<pie_>
*trips
<rqou>
that's really hard to figure out :P
<rqou>
i don't think you understand
<pie_>
i havent the faintest clue honestly :P
<mtp>
rqou, that's fucked
<mtp>
is this like, retrofitted 2-wire systems?
<rqou>
touching the meraki ms switch doesn't do anything
digshadow has quit [Quit: Leaving.]
<lain>
mtp: ask him to show the pictures
<mtp>
lain, i was in a house once that had knob&tube wiring
<mtp>
and, like, the electrician pulled off a plate in the kitchen, right?
<mtp>
he calls me over and does that "what the FUCK" whistle
<mtp>
one of the cloth-insulation wires is _nailed into_ the metal box
<mtp>
now, every time i tell this story irl, some smartass is like "well that's fine, it's the ground wire, right?"
<mtp>
NO
<mtp>
THIS WAS A TWO-WIRE SYSTEM
<mtp>
IN A TWO-WIRE SYSTEM THERE IS NO REASON FOR ANY OF THE WIRES TO BE TOUCHING ANYTHING METAL
<qu1j0t3>
mtp: o/
<lain>
mtp: oh god
<nats`>
but if there is a metal casing there should be no two wire system !
<nats`>
metal casing => ground wire
<mtp>
this was literally unmaintained since the 1940s
<mtp>
also hi qu1j0t3
<nats`>
so I wouldn't touch anything with cutting eletric arrival :D
<lain>
in other "shit is royally fucked" news, a steak&shake restaurant here has been shut down for the third time in under 2 years
<balrog>
lain: violations?
<mtp>
STTLWA only recently got a steak&shake
<lain>
the health department is threatning to close the location for good. it would be the first time this county has ever had to close a chain restaurant
<lain>
balrog: yes
<balrog>
lol
<lain>
balrog: bad ones
<balrog>
how bad?
<lain>
they won't share specifics other than "it's bad"
<lain>
triply so since this is the third time, after multiple probation periods
<lain>
after the second one, S&S corporate fired the manager and replaced him, but apparently the new one is just as bad lol
<rqou>
i mean, you're talking about a government entity in Middle-of-Nowhere, USA :P
<lain>
yeahhh
<pie_>
whatcha gonna dooo
azonenberg_work has joined ##openfpga
<balrog>
lain: yikes!!!
<lain>
"The health department ordered the restaurant closed on Oct. 19 after inspections on Oct. 16 and Oct. 19 uncovered violations involving incorrect temperature readings for holding food, multiple equipment issues related to temperature control and equipment maintenance that was ordered but not done."
<lain>
"During the Oct. 16 routine inspection, the location was cited for 12 critical health code violations, 16 non-critical violations and four repeat violations. The follow-up inspection on Oct. 19 found five critical violations, eight non-critical violations and four repeat violations."
<lain>
so basically they give no fucks
<nats`>
nice
<qu1j0t3>
wow.
<nats`>
need to loose some weight ?
<qu1j0t3>
there's ya nanny state for ya
<nats`>
go there 3 time a week
<nats`>
puke for 2 month
<cr1901_modern>
wow...
<qu1j0t3>
seriously though regulations are just getting in the way of profit
* qu1j0t3
runz and has the runz
<balrog>
qu1j0t3: nice sarcasm there
<qu1j0t3>
balrog: Guilty
<lain>
lol
<nats`>
yay stop limiting car consumption :p
<nats`>
let's all get a shiny SUV with 40L/100km :D
<lain>
"The Ireland Road restaurant has been cited by the county health department 129 times from 2010 through June 2015, including 38 critical violations. Of those violations, the most common involved cleanliness of appliances and equipment in the kitchen. The next most common violation related to the "holding temperatures" of food, according to health department records."
<lain>
lol
<lain>
I remember working at kroger meat department and they instructed me -- my manager instructed me -- to lie on the record sheet about the freezer temps
<lain>
because "it's a hassle to read the gauge"
<balrog>
review from 4 months ago: "**Been there once since latest shutdown from health board 9/8/16***** decided I'd give it a try since supposedly they have new management. NEVER again! Got the chicken taco salad and chili with cheese and onion through the drive thru. I sat for 20 minutes then was asked to pull up. Sat for another 20+ minutes. I was annoyed but thought wow at least my food will be fresh. WRONG!!!! Chili was cold and I mean cold. My
<balrog>
salad...... the chicken wasn't cooked fully! It was not pink but it was a gob of solid that could not be pulled apart and cold! I called the steak and shake and asked for a manager. When he gets on I explain everything. He said miss our chicken is precooked and hung up. Bull crap. That was semi raw chicken. They are going to end up killing somebody one day."
<rqou>
wow, the lb4m firmware manages to kinda look like cisco/netgear's, except without consistent names and lacking UX improvements :P
<lain>
I raised it with another manager, who explained to me that I can only really escalate that to the union, and my manager is the local union rep, so I'd have to go over his head to the regional union rep, which would almost 100% guarantee being fired as soon as he found out
<balrog>
nice that managers are part of the same union...
<balrog>
/s
<lain>
yah
<lain>
and, wow @ that review lol
<balrog>
(google)
<lain>
there was a video that went viral locally here at a taco bell I used to frequent... of a mouse running around on the counter lol
<lain>
the manager runs out and tries to catch it
<balrog>
lain: yelp reviews are just as bad
<balrog>
"I am so sick of this place I will never come to this one again. I have done gave this place a chance after the last time when I found a unknown object in my food and they sent a gift card as a apology. Some food was burned, cold, half there and missing. "
<lain>
all the fast food places around here are reducing their hours and generally dropping in quality, apparently there's a complete lack of useful employees
<rqou>
so apparently the lb4m will change inband management vlans the instant you hit enter on the command
<rqou>
that seems very useful :P
FiveBroDeepBook has joined ##openfpga
digshadow has joined ##openfpga
FiveBroDeepBook has quit [K-Lined]
<lain>
I don't know what I'm going to gain by getting a native ipv6 /56 allocation
<rqou>
meh, i've gotten higher than that on a campus wired port :P
m_w has quit [Quit: leaving]
Hootch has joined ##openfpga
discrttm is now known as nonlinear
<lain>
haha
<pie_>
mybackbone is bigger than urs
<pie_>
kek
<pie_>
i mean not really, im jus sayin
m_w has joined ##openfpga
<rqou>
hmm iperf in tcp mode: 8gbit/s
<rqou>
udp mode: 1mbit/s
<rqou>
not sure where the problem is here
<rqou>
peaking at 9.4gbit/s with multiple threads
<rqou>
good enough i suppose?
<lain>
lol
<lain>
9.4gbit/s with udp?
<lain>
or is udp still stuck at 1mbit/s
<rqou>
udp is still stuck
<rqou>
whatever
<rqou>
maybe iperf problem, maybe firewall problem
<rqou>
punting that issue till later
cr1901_modern has quit [Ping timeout: 264 seconds]
<rqou>
azonenberg: so i just ran iperf continuously for 10 minutes (650 gigabytes) and using the fs.com transceivers the card reports zero bit errors
<rqou>
works for me?
<rqou>
15m of OM4 here
<azonenberg_work>
rqou: :)
<azonenberg_work>
rounding to one error in 650 GB
<azonenberg_work>
<1 *
<azonenberg_work>
that's <1 error in 5.2 Tb
<azonenberg_work>
Which comes out to a BER of better than 1E-12
<azonenberg_work>
and closer to 1E-13
<lain>
rqou: I seem to recall having weird udp perf issues in iperf, and I think I found that freebsd significantly rate-limits udp
<lain>
but it wasn't 1mbit/s bad
<lain>
I don't remember what it was :P
<azonenberg_work>
rqou: grr you, dig, and davidc___ are making me look bad
cr1901_modern has joined ##openfpga
<azonenberg_work>
there's folks with 10gbit ethernet and SEMs here
<azonenberg_work>
at home
<azonenberg_work>
and i dont have either :'(
<cr1901_modern>
must be nice to have money...
<rqou>
apparently if you want 10gbe for cheap you can go on ebay and order some old mellanox connectx-2 cards
<rqou>
they're apparently around $30
m_w has quit [Quit: Leaving]
<azonenberg_work>
rqou: my problem right now is that i have fiber and 1g optics (and 40g optics, lol)
<azonenberg_work>
But i dont haev enouhg pcie slots
<azonenberg_work>
which means new motherboards
m_w has joined ##openfpga
<azonenberg_work>
which means new cpus and new ram
<rqou>
heh, i tried to put the intel x520 card on a bay trail atom just for lulz :P
<rqou>
even with enough slots it doesn't work
<rqou>
not enough pcie bridge window memory space?
<rqou>
the driver was complaining a BAR didn't fit
<davidc___>
cr1901_modern: s/money/luck in most cases
<azonenberg_work>
yeah dig got his sem for like $3K i think
<rqou>
weird oem x520 cards are about $130
<davidc___>
and its also definitely not the tools, and much more "how/how much you use them"
<azonenberg_work>
just dumb luck at an industrial auction
<azonenberg_work>
found it in working condition fully assembled and ready to go
<davidc___>
I mean, I have a SEM, but have done essentially 0 chip hacking (other than some basic imaging) due to ENOTIME
<cr1901_modern>
davidc___: Fair enough. I'd rather have time than money, tbh
<cr1901_modern>
No point in having excess money if you don't have time
* cr1901_modern
's law: time > money
<davidc___>
cr1901_modern: eh; mostly its ENOTIME due to: $normal_available_time/$number_of_projects is approaching zero
<davidc___>
as the number of projects approaches infinity
<azonenberg_work>
lol yes
<azonenberg_work>
i have so much yak fur and so many dull razors
<cr1901_modern>
davidc___: Tbh, this is why I'm often reluctant to expand my horizons
<cr1901_modern>
if I context switch from a project, often I won't come back to it for months
<lain>
azonenberg_work: imma make you look bad too when I get my 100Mbps wireless link to the DC up
<azonenberg_work>
lol
<lain>
the dishes can link at 300Mbps but they only have one 10/100 ethernet port :<
<lain>
can always upgrade later to something with gigabit
<rqou>
lain: does the DC allow any customers to just install random antennas and crap on the roof?
<rqou>
or just your special unofficial relationship?
<lain>
rqou: they're also a WISP, so they will if you pay money to connect
<lain>
but since I already pay for a gigabit switch port and rack space there, I'm hoping mike will install my dish for a case of beer or something
<lain>
I have literally no idea how much he likes or dislikes climbing the tower to install shit, he might not do it unless it's official, at which point it's up to jay or joe to determine what/if I have to pay :P
<rqou>
hmm, comcast seems to have fixed their dhcp mtu 576 issue that existed at one point
dingbat has quit [Quit: Connection closed for inactivity]
m_t has quit [Quit: Leaving]
<pie_>
i know theyre really old but are there any main differences between spartan 3e and spartan 3an?
<azonenberg_work>
3an is a 3a with a spi flash wirebonded inside the package
<azonenberg_work>
3a vs 3e i dont remember the differences
<lain>
I think 3a has more dsps or something?
<lain>
it's been so long
<cr1901_modern>
I have one S3 board. I mainly have it b/c it has 5v tolerant I/O (via clamps)
<pie_>
whats a DCM
<lain>
digital clock manager
<azonenberg_work>
pie_: poor man's PLL
<lain>
^
<azonenberg_work>
cheaper, less die area, more jitter and noise
<pie_>
oh ok ( i still need to look up how plls work)
<cr1901_modern>
You mean, the Best Thing Since Sliced Bread
<pie_>
heh
<pie_>
ok thanks
<cr1901_modern>
They're plentiful compared to PLLs
<cr1901_modern>
you get two (TWO!!) for each PLL
<pie_>
i could probably get blinken leds pretty fast if only i had any idea how to learn to use xilinx thingy
<pie_>
i want to do 2 (two) things for starters: 1)synthesize HDL to some visual gate-ish representatio so i can see that it synthesized to something sane
<pie_>
2) make the thng go
<pie_>
:(
<azonenberg_work>
pie_: you can view a post-synthesis netlist in ISE
<qu1j0t3>
yeah, or Quartus in Altera world.
<lain>
azonenberg_work: so, not necessarily of interest to you, but a good sign for the industry: sony announced a new cellphone (1/2.3") 3-layer stacked image sensor - it's backside illuminated CMOS on top, DRAM middle, logic bottom. standard MIPI, but it can capture 1000fps 1080p to the internal dram, and has 1/120th second rolling shutter, eliminating rolling shutter artefacts for typical usage
<pie_>
yeah im in xilinx world because thats what i borrowd from theuniv
<qu1j0t3>
pie_: you can also do it with free tools, i think this conversation came up a few weeks ago
<qu1j0t3>
pie_: I mean... have you tried?
<cr1901_modern>
I just remembered... I wanted to use my Spartan 3 board as a logic analyzer, but either qu1j0t3 or felix_ told me not to directly connect the signals being measured to the I/O pins... and I don't remember why
<qu1j0t3>
cr1901_modern: I also want to do this, but yeah, you definitely don't want to connect directly, as I understand it. I'll leave it to others to explain the technical reasons and I'll also watch
<pie_>
*speed
<cr1901_modern>
I don't remember who told me not to. I *think* it was felix_ then.
<qu1j0t3>
yeah we had a discussion last year i think and i forget the detail.
<qu1j0t3>
s.
<pie_>
well what if you get bad vltages?
<pie_>
also line noise and heck knows
<lain>
cr1901_modern: basically you want protection circuitry, and probably some level translating schmitt-trigger buffers so you get clean edges even on slow rise/fall signals
<pie_>
metrology is complicated :x
<cr1901_modern>
my board already has voltage clamps
<cr1901_modern>
ahhh, but they aren't schmitt-triggers
<lain>
or use comparators or similar and supply them from a DAC so you can set the threshold voltages
<lain>
lots of ways to do it
<cr1901_modern>
lain: Fair enough, but the conversation got quite a bit in-depth, and I was just reminded that I'd like to continue it :P
<qu1j0t3>
pie_: Did you ever find a text with exercises?
<qu1j0t3>
cr1901_modern: I want to do something along these lines this year
<cr1901_modern>
which isn't good if I can't remember who I was having the convo with :)
<qu1j0t3>
cr1901_modern: so thanks for bringing it up again
<lain>
hehe
<cr1901_modern>
qu1j0t3: Np... thank pie_ for bringing up Spartan3 :P
<pie_>
qu1j0t3, i kinda forgot aboot it cuz i had to switch to exams, but there were some at the end of the book
<rqou>
because all vlans have the same mac address
<pie_>
lain, wut is that
<jn__>
an FPOA seems to be just what's now called an FPGA
<lain>
jn__: not quite
<lain>
jn__: the FPOAs I saw back when they existed were prebuilt logic blocks (as opposed to the more flexible LUTs of fpgas), like you'd have ALUs, DSP blocks, etc... and you just control the interconnect... but they ran at several GHz
<lain>
so, less flexible, but muuuch faster
<jn__>
ah, that's nice
scrts has quit [Ping timeout: 256 seconds]
<azonenberg_work>
yeah FPOAs seem like basically very coarse grained fpgas
pie_ has quit [Ping timeout: 240 seconds]
scrts has joined ##openfpga
<rqou>
hrm, i think my imac g3 needs a new battery
<rqou>
every time i boot it it now needs an embedded controller reset
dingbat has joined ##openfpga
<mtp>
macs get real surly when their batteries are dead, yeah
<rqou>
yeah, and this is an ancient ppc mac too
<rqou>
so its battery is probably close to dead to start with
<felix_>
rqou: which chipset does the mellanox connectx-2 card use? will those work without having to mess with some out of tree drivers?
<rqou>
um, it uses the mellanox chipset? :P
<rqou>
idk how the details work
<rqou>
i think there's an in-tree driver, but generation 2 might be getting dropped soon
<felix_>
cr1901_modern: problem with connecting probes directly to an foga is that the fpga inputs aren't that hard to destroy and so you want some input protection circuitry between the probes and the fpga
<felix_>
rqou: hm, so i better din't get some of those cards
<felix_>
cr1901_modern: with some tricks you can build an ok-ish input stage for cheap, but there's always a trade-off
<rqou>
hmm actually it seems it's still supported
<rqou>
maybe the series even before that is getting dropped?
<azonenberg_work>
felix_, cr1901_modern: This is where my starshipraider project comes in
<rqou>
mellanox cards are a bit weird though
<rqou>
they're infiniband cards with ethernet duct-taped on
<azonenberg_work>
Among other things i'm making an input stage that's +/- 12V tolerant and can run at 1.2 to 5V logic levels
<rqou>
the linux kernel driver is "mlx4" if you want to look into it some more
<rqou>
i assume the driver is unlikely to be removed but just not get new features added