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<wpwrak>
there are two "receivers"
<DocScrutinizer>
fig7 is completely different in that respect
<wpwrak>
i think "receiver" is actually source. and "receiver (2)" is the actual receiver.
<wpwrak>
fig. 5 is bidirectional. and confusing ;-)
<wpwrak>
yes, fig 7 is cool. just terminate in the middle ;-)
<DocScrutinizer>
wpwrak: whatever fig5 is meant to be, the schematics are clearly more like fig2 rather than fig7, regarding terminating impedance on both ends
<DocScrutinizer>
whatever that 18R in fig2 right end means, it's there
<DocScrutinizer>
their simulation net in fig7 is completely messed up regarding that
<DocScrutinizer>
err s/fig2/fig5
<wpwrak>
they admit that: "From the above discussion this is not an optimal configuration."
<wpwrak>
(page 4. right column)
<wpwrak>
they may be concerned that people trying to achieve a perfect but complicated termination would do more damage than good :)
<DocScrutinizer>
they picked that compromise solution for sake of BOM
<DocScrutinizer>
as they state somewhere
<DocScrutinizer>
this doesn't put any sense into fig7 for me
<DocScrutinizer>
as this sim net assumes termination impedance of infinite + 5pF
<DocScrutinizer>
or zero, which wouldn't make any more sense
<DocScrutinizer>
actually the sim net is garbage, they neither placed any proper source symbol in there, nor a proper sink that in any way siggests what impedance (4) shall have
<DocScrutinizer>
*usually* you assume impedance of zero for sources and infinite for sinks, in such cases
<DocScrutinizer>
zero for surce is in line with 15R at left side, which models the actual driver impedance
<DocScrutinizer>
I don't see anything at right side modelling the sink impedance (unless we assume the chip actually has near to infinite resistive component, and 5pF capacitive component)
<DocScrutinizer>
actually this might match the real chip's input characteristics
<DocScrutinizer>
for me the 7nH and 5pF on right side fig7 are similar to left side, and indeed part of the chip pin sim
<DocScrutinizer>
looking into fig9* you see the effect of this mismatching: overshots
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<DocScrutinizer>
wpwrak: also note please that this is an optimization for DQ line, aka bidir
<wpwrak>
yes. for unidirectional, they use more traditional termination
<DocScrutinizer>
:nod:
<wpwrak>
which makes me wonder ... do we ? checking ..
<DocScrutinizer>
at least for unidir you should stick with fig2
<DocScrutinizer>
which directly leads to a series R for source, and a parallel R to GND for sink
<DocScrutinizer>
also note that even a transmission line with massive mismatch at one end still can work reasonably well when other end is optimally matched
<wpwrak>
micron actually recommend to do the same for bidir and unidir
<DocScrutinizer>
there will be reflections (aka overshots) but they get killed after one travel along the line
<wpwrak>
yeah
<wpwrak>
transmission lines are fun :)
<DocScrutinizer>
and actually I think that's what they do with their center termination
<wpwrak>
yup. sounds like it's that
<DocScrutinizer>
anyway, doesn't that give you an invincible desire to do your own spice tests?
<wpwrak>
so totally not ;-))
<DocScrutinizer>
hehe
<DocScrutinizer>
they offer ready made spice data ;-)
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<DocScrutinizer>
>> Micron provides both IBIS and Spice models to help in this area (see ww.micron.com/models).
<wpwrak>
feel free ;-)
<DocScrutinizer>
I'm actually tempted, alas it's again almost midnight here
<DocScrutinizer>
I start to hate this making_money
<wpwrak>
having a dayjob kinda sucks ;-)
<wpwrak>
and it's not the money. it's the day :)
<DocScrutinizer>
there's a design glitch in this big simulation
<DocScrutinizer>
maybe the parameter "MONEY" been a totally useless change to the original setup
<wpwrak>
mmh ? what original setup ?
* DocScrutinizer
wanders off, searching for the RED PILL
<wpwrak>
ah, the hour of the tranquilizer :)
<DocScrutinizer>
nah, RED PILL isn't tranquilizer, rather a POP on stack
<wpwrak>
return to sleep mode :)
<DocScrutinizer>
but we all learnt from Matrix, that it's a SIM in a SIM in a SIM (btw a concept that's as old as "Welt am Draht" at least)
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<wpwrak>
a film that would have greatly benefited from some cutting :)
<DocScrutinizer>
so maybe not going to take RED PILL will be the more comfortable alternative / the better SIM, despite this MONEY thing
<wpwrak>
heh :)
<DocScrutinizer>
tw as cool as those delay elements in FPGA may be, they need nasty config - I strongly suggest to try and keep traces same length
<DocScrutinizer>
.s/tw/btw
* whitequark
has read 10 lines of backlog
<DocScrutinizer>
whitequark: then yu missed all the good stuff ;-)
<wpwrak>
ah, you've dropped off the cc again
<whitequark>
wpwrak: cc?
<wpwrak>
i forwarded you the missing mails
<wpwrak>
no, DocScrutinizer
<DocScrutinizer>
umm?
<DocScrutinizer>
aah
<DocScrutinizer>
mail
<wpwrak>
whitequark: he prefers if we copy him explicitly on our mails instead of simply subscribing to the list. so every once in a while, the cc: is lost and the thread goes on without him
<wpwrak>
whitequark: then he gets confused when we discuss in a context that has already changed. until someone detects the problem and forwards him what seem to be the missing mails
<whitequark>
hmm, context
<wpwrak>
they're of course unthreaded then, possibly increasing the confusion :)
<whitequark>
DocScrutinizer: looks like your SP gets corrupted sometimes
<whitequark>
and you suddenly find yourself in a middle of a wrong stack frame
<whitequark>
err... recompile yourself with -fstack-smashing-protector ?..
<DocScrutinizer>
no increased confusion here :-D
<DocScrutinizer>
yep, a slightly caring layout should result in a routing that "just works"
<DocScrutinizer>
except for those "differential lines"... o.O - we got any of those?
<wpwrak>
yes, the clock is differential
<DocScrutinizer>
:nod:
<DocScrutinizer>
so you may consider 2-laxered design for those traces
<DocScrutinizer>
2-layered*
<wpwrak>
hmm. just parallel should do the trick. otherwise you need to consider the vias as well
<DocScrutinizer>
you can easily make via length identical
<wpwrak>
but they're on the same side. so one would go down and then up again
<wpwrak>
unless you have a pcb with buried components. that would be fun ;-)
<DocScrutinizer>
2/6 via + trace + 4/6 via, vs n/6 via + trace + (6-n/6) via
<DocScrutinizer>
down and then up, what's wrong about it?
<wpwrak>
but why ?
<wpwrak>
just seems to make things more complicated
<DocScrutinizer>
to do sth about your concerns regarding via length
<wpwrak>
you mean trace
<DocScrutinizer>
nope, via
<wpwrak>
now you lost me :)
<DocScrutinizer>
>>>... otherwise you need to consider the vias as well
<wpwrak>
simplest design: everything on the surface
<wpwrak>
next to simplest: both dive out of the FPGA, then come back up together somewhere
<DocScrutinizer>
as long as your traces are straight line, yes
<DocScrutinizer>
have some bend in them and you run into length issues
<wpwrak>
as long as they are exact copies of each other
<DocScrutinizer>
and 0.5mm i actually a bit demanding
<wpwrak>
yes. different radii would be trouble.
<wpwrak>
they're probably exaggerating ;-)
<wpwrak>
just consider the propagation speed of the signal
<wpwrak>
units 0.5mm/c ps -> 1.667
<DocScrutinizer>
c on PCB is not what you might think it is
<wpwrak>
even if we assume 66% of c, that's merely 2.5 ps
<DocScrutinizer>
>>> Velocity factor is a fractional value relating a transmission line's propagation speed to the speed of light in a vacuum. Values range between 0.66 and 0.80 for typical two-wire lines and coaxial cables
<wpwrak>
that sounds like "chess in hyperbolic n-spaces for dummies" :)
<wpwrak>
see. 2/3 was already a pessimistic estimate.
<DocScrutinizer>
no really, it's nice
<wpwrak>
i think it should be a bit faster on the pcb (if i interpret wikipedia right :)
<DocScrutinizer>
even with extremely slower velocity we get not even in pall park where 0.5mm matters
<wpwrak>
yes, seems to me that way,too
<DocScrutinizer>
DANG
<DocScrutinizer>
0.1ns results in ~0.025mm if my math doesn't suck
<wpwrak>
i think it does :)
<wpwrak>
units 0.1ns*0.66c mm -> 19.786302
<DocScrutinizer>
yeah, sth is wrong with my math
<DocScrutinizer>
my feeling tells
<DocScrutinizer>
1ns = 1GHz
<DocScrutinizer>
GHz wavelength is not sub-mm
<wpwrak>
only for very slow light :)
<wpwrak>
tardions, not tachyons
<DocScrutinizer>
meh, time for zzZZzz
<wpwrak>
sweet suspend ! :)
<DocScrutinizer>
:-)
<DocScrutinizer>
one last thing, I think I heard they built some sort of TL for light, that was actually in range of mm/s
<DocScrutinizer>
also c inside sun is astonishingly low
<DocScrutinizer>
needs several 1000 years to reach surface from center
<wpwrak>
must be a huge traffic jam for those poor photons
<DocScrutinizer>
indeed, it is
<DocScrutinizer>
luckily they can crowd up really dense
<DocScrutinizer>
;-D
<DocScrutinizer>
afaik they won't ever collide with their own kind
<wpwrak>
can't have the same kind of particle at the same place at the same time
<wpwrak>
that's why you never read of, say, rolls royces colliding
<DocScrutinizer>
I think they never are in one place at one time, since Heissenberg
<DocScrutinizer>
but they must have *some* mass. I guess e/c^2
<DocScrutinizer>
so too many of them crowded up in one spot may result in a black hole
<DocScrutinizer>
is there any theoretical upper limit for frequency of electromagnetic waves?
<DocScrutinizer>
IOW what's that radiation that starts where gamma spectrum ends?
<wpwrak>
one period per Planck length ?
<wpwrak>
and only relativistic mass. m0 = 0. or they couldn't travel at c.