00:37 <cr1901_modern> sb0: Why doesn't misoc have a wishbone CDC? Or alternatively: What's your way of handling a CDC over a wishbone bus?

06:42 <larsc> convert to AXI, CDC transfer that, convert back to wishbone ;)

08:24 <sb0> cr1901_modern, misoc only contains stuff that I have needed or that people have contributed

09:16 <cr1901_modern> sb0: Fair. Assuming you're running the CPU bus at a single clock speed, how do you personally handle CDCs on designs with a soft CPU then? Just put the crossing logic *after* the bus using an AsyncFIFO or BusSynchronizer?

09:17 <cr1901_modern> larsc: Assuming you're joking, but it went over my head :P

10:39 <larsc> cr1901_modern: you kind of have to do that anyway

10:39 <larsc> you might not call the signals the AXI names, but they will have a very similar structure

10:40 <larsc> the problem with wishbone is that it has data going in both directions synchronized

10:41 <cr1901_modern> larsc: I've never actually used AXI

10:41 <cr1901_modern> For the time being I'm using the following solution: https://github.com/alexforencich/verilog-wishbone/blob/master/rtl/wb_async_reg.v

10:42 <cr1901_modern> It uses a handshake on the STB signal (why not CYC?) from the master-to-slave direction, which ensures that the data will be held constant long enough in the src domain

10:43 <cr1901_modern> When STB signal makes it past the crossing, we're guaranteed to have had all the other WB signals stable long enough such that metastability can't occur, so we xfer them all at once. At least, that's my understanding.

10:45 <larsc> makes sense

10:45 <cr1901_modern> My question is why did the designer use STB as the handshake signal and not CYC? I guess I could email them to ask.

10:49 <cr1901_modern> I confess I actually don't understand Migen's BusSynchronizer either. sb0, did you write that?

11:27 <larsc> does it toggle?

11:28 <cr1901_modern> larsc: Yes. STB will toggle for pipelined xfers. CYC will be constant for the whole cycle

11:28 <cr1901_modern> ... which I think answers my question

11:36 <cr1901_modern> larsc: Thanks :P. I figured it out w/ that follow up q

15:45 <GitHub182> [artiq] vontell opened issue #659: Lack of information on stacktrace https://git.io/vMb9g

18:37 <GitHub11> [artiq] whitequark reopened issue #656: Default types overridden https://git.io/vMojy

20:03 <cr1901_modern> SO TIL that a Xilinx DCM takes literally hundreds of clock cycles to lock. I learned that because I accidentally set an LM32 design to be held in reset whenever the DCM acheives lock.

20:03 <cr1901_modern> I'm surprised the LM32 got far enough to blink the leds with an unlocked DCM...

20:05 <GitHub162> [artiq] whitequark commented on issue #659: > For exceptions where an operation is attempted between an numpy.int32 and numpy.int64, there is no information (i.e. line number in my code) where the error occurs.... https://git.io/vMNwM

20:36 <GitHub49> [artiq] vontell commented on issue #659: My code begins with this [`initialize-test.py`](https://github.com/vontell/artiq-control/blob/master/samples/repository/initialize-test.py) EnvExperiment. Before line 52, there is mostly just variable declaration, which has compiled fine in the past. On line 52 is a method `rabi.get_photon_windows()`, which I have also run and tested with no trouble.... https://git.io/vMNiN

20:38 <GitHub21> [artiq] vontell commented on issue #659: The ['rotate()` method](https://github.com/vontell/artiq-control/blob/master/samples/repository/rle/pipistrello.py#L208) of `rabi.py` may also be the culprit. https://git.io/vMNPC

20:38 <GitHub183> [artiq] vontell commented on issue #659: The ['rotate()` method](https://github.com/vontell/artiq-control/blob/master/samples/repository/rle/pipistrello.py#L208) of `rabi.py` may also be the culprit. https://git.io/vMNPC

20:44 <GitHub154> [artiq] whitequark closed issue #637: Memory corruption in lwIP https://git.io/v1ldy

20:45 <GitHub107> [artiq] whitequark commented on issue #637: With smoltcp merged this is issue is not present any more. https://git.io/vMNXB

20:45 <GitHub105> [artiq] whitequark commented on issue #647: I believe this issue has been resolved, @jbqubit can you test with ARTIQ master please? https://git.io/vMNXw

20:49 <GitHub179> [artiq] whitequark commented on issue #456: @jordens if you have an easy way to reproduce this bug, can you please check whether it's still present with smoltcp? https://git.io/vMN1R

20:56 <GitHub90> [artiq] whitequark commented on issue #570: We've merged smoltcp, which is released under 0-clause BSD, so the TCP/IP stack is no longer a constraint. https://git.io/vMNMw

20:58 <GitHub131> [artiq] jordens commented on issue #654: It seems to me that we could just mark the coredevice object on the host as "in-use" so that when an RPC comes in from a kernel, the worker handling the RPC can tell straight away that any kernels called (through this reentrant code path) while the coredevice is active are disallowed. https://git.io/vMNDC

21:00 <GitHub166> [artiq] jordens commented on issue #456: I can only try to reproduce #647 which may or may not be the same. https://git.io/vMND9

21:01 <GitHub163> [artiq] whitequark commented on issue #654: It seems better to do this in the RPC protocol because this catches more errors, and simplifies bug reporting for any cause of load failure. https://git.io/vMNDx

21:05 <GitHub145> [artiq] whitequark commented on issue #456: @jordens That's useful too. https://git.io/vMNy0

22:12 <rjo> whitequark: there is only garbage on the terminal. is that related to your uart speed change? did you update the documentation and all the other tools to cope with that change?

22:13 <whitequark> yes. no.

22:14 <whitequark> I wanted to switch the entire thing, starting with misoc BIOS, to 1Mbaud

22:14 <rjo> whitequark: well it doesn't reply to pings. can't say more because there is nothing useful on the console.

22:15 <whitequark> flterm --speed 921600

22:15 <whitequark> hang on, I think I know the cause. did you switch the IP from 192.168.1.50 to something else through the configuration?

22:16 <rjo> this is the aux kc705 .51

22:16 <GitHub36> [artiq] whitequark pushed 2 new commits to master: https://git.io/vMNx1

22:16 <GitHub36> artiq/master 3633671 whitequark: firmware: factor out console and logging from runtime/satman.

22:16 <GitHub36> artiq/master 5604d9b whitequark: firmware: factor out build scripts from runtime/satman.

22:16 <whitequark> right. well. the configuration is currently just ignored.

22:17 <whitequark> I should fix that

22:17 <rjo> whitequark: then we have two boards with the same ip/mac now.

22:17 <whitequark> yup.

22:17 <rjo> whitequark: let's fix that first before we test the other things.

22:28 <GitHub125> [artiq] whitequark pushed 2 new commits to master: https://git.io/vMNjT

22:28 <GitHub125> artiq/master b29e2d5 whitequark: Globally update UART baudrate to 921600.

22:28 <GitHub125> artiq/master e5085c0 whitequark: doc: test mode was removed, clean up.

22:35 <bb-m-labs> build #323 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/323

22:44 <bb-m-labs> build #1227 of artiq is complete: Failure [failed python_unittest_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1227 blamelist: whitequark <whitequark@whitequark.org>

22:52 <GitHub81> [pythonparser] trotterdylan opened pull request #8: Reverse the order of elif clauses in ast (issue #7) (master...master) https://git.io/vMAJA

23:03 <bb-m-labs> build #324 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/324

23:12 <bb-m-labs> build #1228 of artiq is complete: Failure [failed python_unittest_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1228 blamelist: whitequark <whitequark@whitequark.org>

23:39 <GitHub1> [artiq] sbourdeauducq commented on issue #456: @whitequark I'll be in Hong Kong soon, do you want me to connect the KC705(s) through the problematic switch? https://git.io/vMAmv

23:40 <GitHub74> [artiq] whitequark commented on issue #456: @sbourdeauducq sure, let's test this. https://git.io/vMAmZ

23:44 <sb0> cr1901_modern, BusSynchronizer simply guarantees that all the bits it synchronizes form a valid word