sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<GitHub172> [buildbot-config] sbourdeauducq pushed 1 new commit to master: https://git.io/vDTqX
<GitHub172> buildbot-config/master caf951b Sebastien Bourdeauducq: remove migen -> misoc build trigger
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<GitHub80> [buildbot-config] sbourdeauducq pushed 2 new commits to master: https://git.io/vDTm8
<GitHub80> buildbot-config/master 7967634 Sebastien Bourdeauducq: only run gateware simulations on Linux and exclude them from coverage
<GitHub80> buildbot-config/master 1b65b5f Sebastien Bourdeauducq: do not install Migen and MiSoC for Windows tests
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<GitHub> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/657afd770ecd637085fa78b3a0d10cf4098da855
<GitHub> artiq/master 657afd7 Sebastien Bourdeauducq: artiq/test/gateware -> artiq/gateware/test...
<whitequark> sb0: what are next priorities?
<sb0> DMA
<bb-m-labs> build #355 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/355
<bb-m-labs> build #1261 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1261 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<sb0> ffs had a flterm running
<GitHub> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/43aad0914e5e2dca2e4e28271c9c35c3fb0d0fa8
<GitHub> artiq/master 43aad09 Sebastien Bourdeauducq: python3.5 -> python3...
<sb0> I suppose #638 is also quick, and then we can release 2.2
<whitequark> is that the only thing blocking it?
<sb0> yes
<whitequark> ok
<bb-m-labs> build #356 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/356
<bb-m-labs> build #400 of artiq-win64-test is complete: Failure [failed python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/400 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<bb-m-labs> build #1262 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1262 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
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<GitHub130> [buildbot-config] sbourdeauducq pushed 1 new commit to master: https://git.io/vDT3e
<GitHub130> buildbot-config/master f2e1f06 Sebastien Bourdeauducq: fix 7967634
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<GitHub144> [buildbot-config] sbourdeauducq pushed 1 new commit to master: https://git.io/vDT3T
<GitHub144> buildbot-config/master 03d30ef Sebastien Bourdeauducq: fix syntax error
<sb0> bb-m-labs, force build artiq
<bb-m-labs> The build has been queued, I'll give a shout when it starts
<bb-m-labs> build #1263 forced
<bb-m-labs> I'll give a shout when the build finishes
<bb-m-labs> build #357 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/357
<bb-m-labs> build #401 of artiq-win64-test is complete: Failure [failed python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/401
<sb0> fails with test_rpc_timing on win64
<bb-m-labs> build #1263 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1263
<sb0> whitequark, have you tried having more network buffers?
<sb0> *packet buffers
<GitHub> [artiq] sbourdeauducq pushed 5 new commits to master: https://github.com/m-labs/artiq/compare/43aad0914e5e...d8e99492667c
<GitHub> artiq/master f6024b6 Sebastien Bourdeauducq: drtio: fix ad9154 extension registration
<GitHub> artiq/master 3aced46 Sebastien Bourdeauducq: dashboard: report lost connection with master. Closes #602
<GitHub> artiq/master dcea48a Sebastien Bourdeauducq: protocols/broadcast,sync_struct: add disconnect callback
<bb-m-labs> build #358 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/358
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<bb-m-labs> build #402 of artiq-win64-test is complete: Failure [failed python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/402 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<bb-m-labs> build #1264 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1264 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<GitHub> [artiq] sbourdeauducq commented on issue #619: For supporting the Sinara hardware, switches should be capable of data rate conversion, as the AMC-RTM link has lower bandwidth than the backplane links. https://github.com/m-labs/artiq/issues/619#issuecomment-275976487
<GitHub> [artiq] sbourdeauducq commented on issue #619: For supporting the Sinara hardware, switches should be capable of data rate conversion, as the AMC-RTM link has lower bandwidth than the backplane links. https://github.com/m-labs/artiq/issues/619#issuecomment-275976487
<whitequark> sb0: not yet
<whitequark> I should finish that too
<sb0> bb-m-labs, force build migen
<bb-m-labs> build #130 forced
<bb-m-labs> I'll give a shout when the build finishes
<bb-m-labs> build #130 of migen is complete: Failure [failed conda_install_local] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/130
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<GitHub4> [buildbot-config] sbourdeauducq pushed 1 new commit to master: https://git.io/vDTcp
<GitHub4> buildbot-config/master 7589d0e Sebastien Bourdeauducq: install Python 3.5 for migen
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<sb0> bb-m-labs, force build migen
<bb-m-labs> build #131 forced
<bb-m-labs> I'll give a shout when the build finishes
<bb-m-labs> build #131 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/131
<GitHub162> [buildbot-config] sbourdeauducq pushed 1 new commit to master: https://git.io/vDTCO
<GitHub162> buildbot-config/master 9212e70 Sebastien Bourdeauducq: iverilog is not used anywhere
<GitHub> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/7daab07a29bffa02cf61e28e2f3674d1c9745bcc
<GitHub> artiq/master 7daab07 Sebastien Bourdeauducq: drtio: fix syntax/import
<bb-m-labs> build #359 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/359 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<bb-m-labs> build #1265 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1265 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
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<GitHub> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/bff5f1b714238830146d67e376331cc6510881e4
<GitHub> artiq/master bff5f1b Sebastien Bourdeauducq: conda: update migen
<sb0> taking the drtio transceivers to 3gbps is, of course, another shit show
<sb0> sigh
<sb0> _florent_, any update on that awful packet corruption bug?
<sb0> oh, of course, I forgot to update the si5324 settings
<sb0> whitequark, do you still have their tool installed?
<whitequark> sb0: yeah
<whitequark> which settings do you want me to run through it?
<sb0> 150MHz and 50MHz
<bb-m-labs> build #361 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/361
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<GitHub31> [misoc] whitequark pushed 1 new commit to master: https://git.io/vDTRY
<GitHub31> misoc/master b0d940a whitequark: liteeth: make rx/tx slot count configurable.
<whitequark> sb0: in si5324.rs you're using a whole lot of return Err
<whitequark> for this kind of thing panics are preferable
<bb-m-labs> build #198 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/198
<whitequark> to be more specific: in map_frequency_settings.
<whitequark> the rest is fine
<bb-m-labs> build #404 of artiq-win64-test is complete: Failure [failed python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/404 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<bb-m-labs> build #1267 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1267 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<GitHub28> [misoc] whitequark pushed 1 new commit to master: https://git.io/vDT0L
<GitHub28> misoc/master 02884fe whitequark: kc705: forward rx/tx slot count to LiteEthMAC from MiniSoC.
<bb-m-labs> build #199 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/199
<GitHub> [artiq] whitequark pushed 2 new commits to master: https://github.com/m-labs/artiq/compare/9800acea92ba...b95db4fa4eb7
<GitHub> artiq/master b95db4f whitequark: Use four ethmac buffers instead of two....
<GitHub> artiq/master 3a19a9f whitequark: firmware: minor cleanup in board::si5324.
<bb-m-labs> build #362 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/362 blamelist: whitequark <whitequark@whitequark.org>
<bb-m-labs> build #1268 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1268 blamelist: whitequark <whitequark@whitequark.org>
<GitHub> [artiq] whitequark pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/c585784cd9f778c19019fe014311016f3aa2027f
<GitHub> artiq/master c585784 whitequark: conda: bump misoc dependency.
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<bb-m-labs> build #363 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/363
<bb-m-labs> build #405 of artiq-win64-test is complete: Failure [failed python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/405 blamelist: whitequark <whitequark@whitequark.org>
<bb-m-labs> build #1269 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1269 blamelist: whitequark <whitequark@whitequark.org>
<sb0> whitequark, can i use the kc705s?
<whitequark> sb0: yes
<whitequark> btw, enlarging the buffers worked pretty well
<sb0> cool
<whitequark> there are still retransmits, of course, but the situation is significantly less bad
<whitequark> ideally what should happen is rolling back buffers to 2x and then getting data into/out of them by an interrupt
<sb0> how many retransmits are there compared to lwip?
<whitequark> not sure.
<whitequark> does it matter? I was going to implement an atomic ringbuffer anyway, for the UART
<sb0> an atomic ringbuffer?
<whitequark> a ringbuffer with atomic push/pop operations
<whitequark> for use from interrupts.
<whitequark> well, not just atomic but lock-free.
<sb0> well, it matters because there are other things to do, like DMA and this getattr bug
<sb0> a lwip level of retransmits is acceptable for now
<GitHub> [artiq] whitequark commented on issue #647: It now takes 200ms to start a 8KB kernel. There is a number of ways to improve on this number, e.g.:... https://github.com/m-labs/artiq/issues/647#issuecomment-276011630
<GitHub> [artiq] whitequark commented on issue #647: It now takes 200ms to start a 8KB kernel. There is a number of ways to improve on this number, e.g.:... https://github.com/m-labs/artiq/issues/647#issuecomment-276011630
<sb0> whitequark, is that 200ms just for the TCP communications?
<whitequark> sb0: no
<whitequark> 200ms is the retransmit time.
<whitequark> the rest is insignificant
<whitequark> to be specific, it takes 200ms to retransmit and the rest of communication, handling, etc is 27ms
<whitequark> lol what the actual hell
<whitequark> the *entire first packet burst* is just zeroes
<whitequark> ok oh not entire. ELF padding before .text
<sb0> but after the first retransmit, the PC calms down and the next kernels on the same connection don't incur another 200ms?
<whitequark> I don't think so, no
<sb0> okay, good to know
<whitequark> erm
<whitequark> I was unclear. I don't think it calms down.
<whitequark> anyway this ring buffer should not be complex to write at all, I'll hopefully do it next morning
<whitequark> just four CASes
<sb0> how large is the TCP window?
<sb0> how many packets will the PC send without waiting for the first ack?
<whitequark> 64k, same size as the underlying buffer
<whitequark> the problem with setting the TCP window based on ethmac buffer state is it doesn't play well if we have multiple sockets open
<whitequark> and it also doesn't play well with chatter on the interface, e.g. broadcast ARP, ICMPv6, etc
<sb0> so the ISR would copy the packets into some socket-allocated buffer?
<whitequark> a separate buffer
<sb0> or some buffer large enough for a lot of connections/chatter?
<sb0> (some global buffer)
<whitequark> it has to be separate because smoltcp isn't mt-safe/reentrant
<whitequark> you can only really poll it in the main loop, and we don't have any upper bound on the time between polls
<whitequark> actually, I wonder how this affects #407
<GitHub> [artiq] whitequark commented on issue #407: @r-srinivas can you recheck with the latest master? https://github.com/m-labs/artiq/issues/407#issuecomment-276015423
<GitHub> [artiq] sbourdeauducq commented on issue #407: or @dhslichter @dtcallcock https://github.com/m-labs/artiq/issues/407#issuecomment-276015699
<sb0> even with the proper si5324 settings 3gbps is still the same shit
<sb0> sigh
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<whitequark> sb0: so about #638
<whitequark> the root cause is that methods defined *only* on instances are not supported, for a good reason
<whitequark> mh, I guess I could add a special case...
<GitHub> [artiq] whitequark pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/2f37b1d1c0d885638c4c9a77729d470b7df63f71
<GitHub> artiq/master 2f37b1d whitequark: compiler: support methods defined on singleton instances....
<bb-m-labs> build #1270 of artiq is complete: Failure [failed lit_test] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1270 blamelist: whitequark <whitequark@whitequark.org>
<GitHub> [artiq] jordens commented on commit bff5f1b: `conda/artiq-dev.yml` also needs updating https://github.com/m-labs/artiq/commit/bff5f1b714238830146d67e376331cc6510881e4#commitcomment-20659562
<GitHub> [artiq] whitequark commented on commit bff5f1b: @jordens that's four files every time something in migen or misoc is changed. Surely there must be some sane way. https://github.com/m-labs/artiq/commit/bff5f1b714238830146d67e376331cc6510881e4#commitcomment-20659574
<GitHub> [artiq] jordens commented on commit bff5f1b: Five files.... https://github.com/m-labs/artiq/commit/bff5f1b714238830146d67e376331cc6510881e4#commitcomment-20659592
<GitHub> [artiq] whitequark commented on commit bff5f1b: Can you implement that? https://github.com/m-labs/artiq/commit/bff5f1b714238830146d67e376331cc6510881e4#commitcomment-20659603
<whitequark> sb0: hm, what's a function like hasattr() but without considering inherited/class fields?
<GitHub> [artiq] whitequark pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/6acdcbb82aa9a2eaca5550db84f8442053d3449b
<GitHub> artiq/master 6acdcbb whitequark: Fix 2f37b1d.
<GitHub> [artiq] jordens commented on commit bff5f1b: If this hinges on me, sure. But from the looks of it not this week. https://github.com/m-labs/artiq/commit/bff5f1b714238830146d67e376331cc6510881e4#commitcomment-20659847
<GitHub187> [misoc] whitequark pushed 1 new commit to master: https://git.io/vDTMV
<GitHub187> misoc/master 421b197 whitequark: Fix the value of mem::ETHMAC_SIZE.
<whitequark> sb0: what are arb_req and arb_gnt dma csrs?
<bb-m-labs> build #364 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/364
<bb-m-labs> build #200 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/200
<sb0> whitequark, assert arb_req, then wait until you get arb_gnt. then you are permanently controlling (D)RTIO until you deassert arb_req.
<bb-m-labs> build #406 of artiq-win64-test is complete: Failure [failed python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/406 blamelist: whitequark <whitequark@whitequark.org>
<bb-m-labs> build #1271 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1271 blamelist: whitequark <whitequark@whitequark.org>
<whitequark> hmm, what's up with the windows rpc rtt...
<GitHub> [artiq] jordens commented on issue #652: We should not make a release with py36 mandatory before there is a reasonable ecosystem to do most of the day-to-day work in py36, i.e. wait for ContinuumIO/anaconda-issues#1315 https://github.com/m-labs/artiq/issues/652#issuecomment-276033836
<GitHub> [artiq] vontell commented on issue #659: After some debugging, I have narrowed it down to the `rotate()` method:... https://github.com/m-labs/artiq/issues/659#issuecomment-276115995
<GitHub> [artiq] vontell commented on issue #659: I have avoided this error by changing the rotate function to the following:... https://github.com/m-labs/artiq/issues/659#issuecomment-276121543
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<sb0> whitequark, why didn't you simply use a boost converter for the ion gauge hv power supply?
<sb0> couple hundred volts is doable without having to wind a transformer
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<sb0> rjo, do we really need a 50T FPGA on Kasli?
<sb0> and we don't need a si5324 in standalone mode, do we?
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<rjo> sb0: well a spartan6 45 is a very tight fit for two cpus. i figured a 50t would be barely ok.
<rjo> sb0: i'd like to not change kasli too much but alter the design so that it can be run stand-alone. i don't want to add another board to the ecosystem. that's inefficient.
<sb0> we can also DNP stuff or use pin-compatible FPGAs, but I'm not sure if it makes sense at those volumes
<sb0> is it the two CPUs that take all the space in the pipistrello? I thought it was the FIFOs
<sb0> plus SERDES logic