sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<sb0>
oh great, recent versions of vivado segfault when synthesizing
<sb0>
this is a cool new problem
<cr1901_modern>
litescope isn't fast enough?
<sb0>
doesn't have the right features, I need multiple clock domains and cross-domain start/stop triggers
<sb0>
this is a really shitty bug
<cr1901_modern>
"cross-domain start/stop triggers" This sounds nasty. You mean the logic to start/stop is logic in one clk domain, it receives a (delayed) version of data being captured in another domain to determine when to start/stop?
<sb0>
the other way, but yes
<sb0>
well, it captures data in a domain, and takes (approximate) triggers from another
<sb0>
seriously, vivado crashes in the verilog *parser*
<sb0>
how the fuck did they get that wrong
<sb0>
it's mor1kx that crashes it
<cr1901_modern>
clifford has been having trouble getting Xilinx to respond to his bug reports :/
<sb0>
yes. xilinx used to have good customer support via the 'webcase' system, but they closed most accounts a few years ago, including mine
<sb0>
it sounds like vivado chokes on `include "mor1kx-defines.v"
<sb0>
the full path for mor1kx-defines.v is over 100 characters. for lm32_config.v it's under 100 characters. did they write char[100] and strcpy?
<cr1901_modern>
Would you be surprised if that were true?
<sb0>
hmm, that's not the problem
<cr1901_modern>
I wonder if ISE chokes
<cr1901_modern>
(prob not)
<sb0>
stekern, have you tried mor1kx with recent (2016.4, 2016.3) vivado?
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<mithro>
So.. A Record() object -- can you assign to the signals inside it individually?
<mithro>
AttributeError: '_Assign' object has no attribute 'list_clock_domains'
<mithro>
<litex.gen.fhdl.structure._Assign object at 0x2b8e87a120f0>
<mithro>
Hrm....
<mithro>
I've obviously sometime wrong...
<sb0>
mithro, yes
<sb0>
what did you do with the assign object?
<mithro>
sb0: I didn't do anything with an assign object, I assume it is combing from somewhere I'm doing a "record.a.eq(signal)" ?
<mithro>
s/combing/coming/
<mithro>
Sorry, I'm a bit tired, it's something simple I've probably done stupidly - been sick all week while still trying to get things ready for LCA recording
<mithro>
Or actually... It might be coming from the Tristate...
<mithro>
sb0: Let me push this code somewhere so you can shame my terribleness
<GitHub54>
[artiq] sbourdeauducq pushed 1 new commit to master: https://git.io/vM2I7
<mithro>
sb0: Should the specials module prevent you from assigning things to it which aren't specials?
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<stekern>
sb0: I have not
<rjo>
sb0: i checked 2016.3 a while back (the install should still be there on lab). are they both crashing in the same way?
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<GitHub182>
[artiq] jordens commented on issue #654: @whitequark Could we catch this type of invalid indirect calls of kernels through RPCs early so that Aaron would have known what the problem is? https://git.io/vM2z7
<GitHub139>
[artiq] whitequark commented on issue #654: @jordens Not sure about "early" but we could definitely return a cause with the LOAD_FAILED message, which would address this as well. https://git.io/vMas0
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<key2>
hi
<whitequark>
hi
<key2>
I am implementing a single wire protocol like in a xilinx FPGA, but for some reason, when I look at the signal with an osciloscope, the 0 part (gnd) are a bit too high and therefor not detected as 0 on the other side
<key2>
is there a common mistake that could be done that results in 0 being detected as 1 ?
<whitequark>
the pullup is too strong?
<key2>
maybe
<key2>
but i removed pullup
<key2>
on the FPGA side
<key2>
but on the other side in fact there is a pullup
<whitequark>
show the schematic
<key2>
single pin
<key2>
like 1 IO going from FPGA to the other device (+ gnd)
<key2>
no external pullup/down
<whitequark>
you have just said there is a pullup on the other side
<key2>
ah inside the device yes
<key2>
i said that because I see that when I am not connected, it is pulled to !
<key2>
on the left part it is the device speaping, on the right one is the FPGA
<key2>
as you can see, the gnd is not at 0 :(
<sb0>
bah maybe you have contention or something, measure the current, isn't it too high?
<sb0>
I wish I was dealing with *your* bug right now...
<whitequark>
key2: is it even a pullup?
<whitequark>
that looks like a strong 1 drive
<key2>
what would you call a strong 1 drive ?
<sb0>
contention. the other side driving high with a lot of current capability.
<key2>
ok
<key2>
which means I should be using a transistor to force it to 0 ?
<key2>
rather than the FPGA ?
<sb0>
probably not, the reason it is driving is probably because it is trying to send something
<key2>
nah
<key2>
for sure it is not
<sb0>
if you force it to 0 not only will it not work but you can also damage things
<key2>
then consider it is not this
<sb0>
what is this for anyway?
<key2>
its a mux
<sb0>
?
<key2>
basically you send it a special code, and it switches
<key2>
its for a connector to a phone
<sb0>
what mux?
<key2>
proprietary
<key2>
the phone lets you chose the pair (uart, usb, debug, swd...) based on a code you send over this 1 wire protocol
<key2>
but it's weird it could come from contention as this pin is not used to be used for anything else than reading what the right mux should be
<key2>
btw it works fine with a papilio pro but not artix
<key2>
so spartan6 seams to be ok
<sb0>
increase the drive strength
<key2>
aha
<key2>
how do I do that with migen ?
<key2>
MISC ?
<sb0>
Drive
<key2>
thx will give it a try
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<sb0>
whitequark, how is TCP coming along?
<whitequark>
let me push the TCP socket code...
<whitequark>
mh, need to sort out the smoltcp dependency first
<sb0>
okay. please leave it in a branch until the unittests pass - I'm using master for drtio development and lwip is good enough for most of the tests I'm doing