<whitequark>
does that enlarge compile times a lot?
<sb0>
no
<sb0>
interestingly, it makes a difference when compiling on my local rust install (compiled according to the artiq doc)
<sb0>
and zero difference on the buildserver, which is using the conda packages
<sb0>
the way I enabled it is with "[profile.dev] lto = true" in the workspace Cargo.toml
<sb0>
-C lto in RUSTFLAGS fails when it tries to build a rlib
<sb0>
and in other Cargo.tomls it gets ignored
<whitequark>
that works, yes
<rjo>
sb0: no. if you guys want my help, keep me in the loop.
<rjo>
sb0: and have him come to irc or something.
<sb0>
rjo, well, all you've missed is some wrong versions of binaries getting flashed, then his clock frequency was wrong (and that caused the SERDES PLL lock failure), after he fixed that it's "JESD ready" not coming up
<sb0>
he increased the clock signal amplitude too
<sb0>
just told him to come to IRC
<rjo>
ok. iirc i wrote down the desired power in README_PHASER
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<jbqubit_>
Hello
<rjo>
hello joe.
<jbqubit_>
Did SB forward you the transcript of our google hangout discussion?
<rjo>
i don't see it.
<jbqubit_>
rjo: I just sent by email
<jbqubit_>
see signal
<jbqubit_>
also
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<jbqubit_>
Hi rjo
<rjo>
jbqubit_: works. what do you want me to do? what's the status?
<jbqubit_>
Status is.... I can locally build artiq master and flash kc705.
<jbqubit_>
J1 clock is confirmed 300 MHz, +11 dBm
<rjo>
and?
<rjo>
does it timeout on jesd enable?
<rjo>
i.e. jesd ready timeout?
<rjo>
well i can try a few things. but probably only significantly on saturday. i have a few proposals to write.
<rjo>
i would/will first try f5f6622 which is the latest version i checked.
<jbqubit_>
OK. I'll leave system up and running on Saturday. With clock applied.
<jbqubit_>
asdf
<jbqubit_>
d
<jbqubit_>
ttyUSB0 and ttyUSB1 are connected to kc705
<rjo>
ok
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