azonenberg_work has quit [Ping timeout: 260 seconds]
azonenberg_work has joined ##openfpga
DingoSaar has joined ##openfpga
laintoo has quit [Ping timeout: 260 seconds]
Zarutian has quit [Quit: Zarutian]
amclain has quit [Quit: Leaving]
DingoSaar has quit [Read error: Connection reset by peer]
pie_ has quit [Ping timeout: 240 seconds]
DingoSaar has joined ##openfpga
scrts has quit [Ping timeout: 240 seconds]
scrts has joined ##openfpga
_whitelogger has joined ##openfpga
DocScrutinizer05 has quit [Disconnected by services]
DocScrutinizer05 has joined ##openfpga
_whitelogger has joined ##openfpga
m_t has joined ##openfpga
laintoo has joined ##openfpga
mifune has joined ##openfpga
mifune has joined ##openfpga
lexano_ has quit [Ping timeout: 268 seconds]
<
azonenberg>
Grrr formal stuff is super useful but also a
*pain* in the behind
<
azonenberg>
I'm trying to prove logical equivalence between two modules
<
azonenberg>
quite small, basic FIFOs
<
azonenberg>
but one is based on ram + pointers and one is based on shift registers
DingoSaar_ has joined ##openfpga
<
azonenberg>
the different internal structure means i cant just have an "assume" constraint that makes them always equal
DingoSaar has quit [Ping timeout: 252 seconds]
_whitelogger has joined ##openfpga
mifune has quit [Ping timeout: 240 seconds]
Bike has quit [Quit: leaving]
pie_ has joined ##openfpga
pie_ has quit [Ping timeout: 260 seconds]
<
X-Scale>
I was just reading about some Stratix 10 specs. Impressive computing power :o
scrts has quit [Ping timeout: 260 seconds]
scrts has joined ##openfpga
scrts has quit [Ping timeout: 240 seconds]
scrts has joined ##openfpga
Hootch has quit [Ping timeout: 268 seconds]
Hootch has joined ##openfpga
talsit has left ##openfpga [##openfpga]
mifune has joined ##openfpga
talsit has joined ##openfpga
mifune has quit [Ping timeout: 255 seconds]
mifune has joined ##openfpga
mifune has quit [Ping timeout: 255 seconds]
mifune has joined ##openfpga
mifune has quit [Ping timeout: 240 seconds]
m_t has quit [Quit: Leaving]
mifune has joined ##openfpga
mifune has joined ##openfpga
mifune has quit [Ping timeout: 255 seconds]
m_t has joined ##openfpga
DingoSaar_ is now known as DingoSaar
wpwrak has quit [Read error: Connection reset by peer]
wpwrak has joined ##openfpga
Bike has joined ##openfpga
scrts has quit [Ping timeout: 258 seconds]
scrts has joined ##openfpga
lexano has joined ##openfpga
scrts has quit [Ping timeout: 258 seconds]
scrts has joined ##openfpga
DingoSaar has quit [Read error: Connection reset by peer]
Zarutian has joined ##openfpga
pie_ has joined ##openfpga
forrestv has quit [Ping timeout: 258 seconds]
forrestv has joined ##openfpga
clifford has quit [Ping timeout: 260 seconds]
seu has quit [Remote host closed the connection]
m_t has quit [Quit: Leaving]
scrts has quit [Ping timeout: 240 seconds]
pie_ has quit [Changing host]
pie_ has joined ##openfpga
scrts has joined ##openfpga
Hootch has quit [Read error: Connection reset by peer]
eduardo has joined ##openfpga
m_w has joined ##openfpga
scrts has quit [Ping timeout: 255 seconds]
scrts has joined ##openfpga