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<pointfree> cyrozap and others: The PSoC HC and HV switching matrices look like circular permutation matrices to me: http://odroid.0xffffffff.in/~deploy/psoc-switching/switching.txt <---- routing of a UDB pair (HC and HV are shown)
<pointfree> You will need to make your text size as small as possible and expand the browser window to larger than your screen size to view the ascii diagram on a laptop. Each line is 1377 characters wide.
<pointfree> Next step: Find the characteristic polynomials of HVA, HVB, and HC.
<cyrozap> pointfree: You can also just use `less -S switching.txt` to view the file :)
<cyrozap> I'll see if I can render it as an SVG for easier viewing.
<cyrozap> pointfree: Is this generated from your code?
<jn__> damn, i need a screen with more pixels
<rqou> er, what exactly am i looking at?
<pointfree> cyrozap: this is from psoc-cli-tools (p3archdump.txt)
<rqou> what needs to be reduced to characteristic polynomials exactly?
<pointfree> rqou: The HC and HV switching matrices. There are rotations (permutations) but they should be expressible with simple polynomials instead of a giant tables. http://odroid.0xffffffff.in/~deploy/psoc-switching/switching.txt
<rqou> yeah, i'm looking at the table but i know so little about the architecture i'm not sure what's happening
<rqou> e.g. i have no idea what the numbers at the left/top are for and what circles represent
<pointfree> rqou: Signals can come in through the tops and bottoms of either HV tiles, and then through the HC tiles, and then through the top or bottom of the HC into a UDB or DSI peripheral (through PI tiles, aka Port Interface). The o's are switches.
<pointfree> HC switching works pretty much the same as HV switching except for the pattern.
<pointfree> diagonal o's connect to different horizontal wires (see the patent images).
<rqou> so the o's in your text file are "possibly-connected points?"
<rqou> i'm still not 100% sure what you're trying to represent with a polynomial
<pointfree> o's are switches. If a switch is connected, it routes the horizontal signal to the vertical wire, and then through a PI tile which looks like this: https://raw.githubusercontent.com/wiki/azonenberg/openfpga/images/US08026739-20110927-D00017.png
<pointfree> Routing works by short circuiting on the PSoC. Switches in series can be viewed as AND'ing together whatever they are vertically wired to. Switches in parallel OR together whatever they are wired to.
<cyrozap> pointfree: Run this command to generate a nice HTML file: `cat <(echo "<html><body><pre>") switching.txt <(echo "</pre></body></html>") > switching.html`
<rqou> ah so this routing logic is kinda like "a weird PLA but not everything is connected to everything else"
<pointfree> Looks better now.
<rqou> pointfree: i'm not sure what you're trying to represent with permutations? the sizes of the inputs/outputs to these blocks aren't the same?
<pointfree> The HV tiles have a pattern that repeats and wraps around mod 16.
<pointfree> The HC tiles have some kind of pattern that also repeats and wraps around, but maybe not mod 128.
<rqou> aah i see what you're trying to do
<rqou> i think?
<pointfree> rqou: I'm looking to represent the pattern of switches with a formula such that given a horizontal wire, map to its vertical wire(s), and given a vertical wire, map to it's horizontal wire(s).
<rqou> what about when there are multiple wires?
<pointfree> rqou: For the purposes of routing, I would represent those as being AND'd together. My routing algorithm (for gelFORTH) is currently about finding minimal routes by way of minimizing Boolean expressions. Although, I'm not yet sure how this will be done on the yosys side.
<pointfree> By the way, even numbered vertical wires map to the upper blocks and the odd numbered vertical wires map to the lower blocks. The rows of DSI routing blocks on the top or bottom of the UDB array will not have either the lower or upper directions implemented depending on whether they are on the top or bottom row.
<pointfree> The o's represent bits in the HC and HV configuration registers. These switches correspond to bits numbered from left to right, and then top to bottom on a given switching matrix.
<pointfree> ....also there is some mirroring action going on with the switch to HC register bit mapping.
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<pointfree> I should update the diagram with the HC <---> PI/UDB mappings on the tops and bottoms of the HC tiles. I have those mappings for the PLD's and datapaths of the UDB's so far....
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<pointfree> cyrozap: It would indeed be nice to have an SVG for easier viewing. Thanks for the "less -S" protip, btw.
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<flaviusb> whitequark: If you are in the mood for anime cancer, Eromanga Sensei is new this season. It looks like a modern remake of Oreimo.
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<nats`> why the hell there is no additive blending in matplotlib
<rqou> because matplotlib sucks :P
<lain> flaviusb: thanks for reminding me of eromanga sensei, forgot to put it on my crunchyroll queue. just watched the first ep, definitely has a lot of oreimo influence
<nats`> rqou maybe but taht's the only plotting solution in python for easy use
<nats`> I'll end with a graphic buffer if it continues and I don't want that
<rqou> I know, I've complained about this but never got around to dealing with it
<nats`> someone published a code but it's a mess
<nats`> let's go with basic blending
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<whitequark> flaviusb: that's not anime cancer, that's like, anime methylmercury
<whitequark> i don't have enough layers of irony allocatable in my brain to watch oreimo
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<nats`> hehe my eye python script work and I think I found a proof of metastability on my spartan 6 :)
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<azonenberg> nats`: :D
<nats`> I found few hundred of ps where the output starts to be weird
<nats`> like skipping bit or weird amplitude :)
<nats`> did you see twitter posts
<azonenberg> Nice
<azonenberg> and not yet
<nats`> BRB
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<pointfree> sixels are turning out to be an easy, one-off, and convenient way to display a bitmap image of an entire fpga's switching to an xterm window in one eyeful. I think it should come in handy for displaying a bitstream as a bitmap image in an xterm as well... I can see this being useful for diffing bitstreams as well.
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<pie_> pointfree, screenshot? :333
<pointfree> pie_: For now I just output a black square for each "." (piece of wire) in the ascii diagram and a white square for each "o" (a switch). http://odroid.0xffffffff.in/~deploy/psoc-switching/sixels-and-bitstreams/hvb_l-hc-hvb_r.png
<pointfree> I would like to vary the shades and colors by tile etc next.
<pie_> hey, i got into science so i could make pretty pictures
<pie_> (jk)
<pointfree> :)
<pointfree> Also, diffing of bitstreams and filtering with a constraint and variance pair.
<pointfree> On #erights I told Zarutian about a small discovery I made: representing a data structure such as a graph with just two numbers, constraint and variance. I think interactively filtering bitstream bitmaps could be an opportunity to use this.
<Zarutian> pointfree: that might be. But I am rather unfamiliar with the usual layout of bitstreams
<flaviusb> whitequark: For some reason I had you cached as the user that had written up a complete total ordering of all Oreimo like anime, with Oreimo at the top - the bar being pretty low, due to the obvious publisher and distributer aversion to that kind of anime. I think it came up in a discussion of OniAi. But it wouldn't be the first time I mistook two completely different people for each other, with vaguely embarrassing results.
<whitequark> flaviusb: you had me as what
<whitequark> I haven't even *watched* oreimo
<whitequark> did you maybe think of @alt_kia
<flaviusb> whitequark: I blame hash collisions.
<whitequark> she IS into that whole thing
<whitequark> and a few more things I wouldn't even mention lest I leak the fact that I'm aware of them
<flaviusb> Heh.
<flaviusb> So the question is, which silicon/reversing/etc channel was I hanging out in that alt_kia was also hanging out in where this topic of conversation could have come up... ?
<whitequark> I don't know and the question disturbs me
<whitequark> :p
<flaviusb> This is why I hate suddenly losing my exocortex state.
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