<azonenberg>
Beginning some work on timing characterization
<azonenberg>
Should be fun
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<azonenberg>
But i dont know if my current devkits are well suited to the task
<azonenberg>
I may have to do some custom boards with buffers etc
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<openfpga-github>
[openfpga] azonenberg pushed 3 new commits to master: https://git.io/vSPqh
<openfpga-github>
openfpga/master 0bdfb95 Andrew Zonenberg: gp4tchar: Added more status prints
<openfpga-github>
openfpga/master 06bd916 Andrew Zonenberg: Initial version of gp4tchar wrapper app
<openfpga-github>
openfpga/master 930681c Andrew Zonenberg: Updated to latest logtools
<azonenberg>
Ok so this was a start, i have an app that brings up the devboard in a minimal clean-slate state
<azonenberg>
with I/O active but does not detect the chip etc
<azonenberg>
So it works with the zif socket empty or even missing
<azonenberg>
Next step, loop back a bunch of pins on the board and measure round-trip delays from the FPGA
<DocScrutinizer05>
which board?
<azonenberg>
DocScrutinizer05: greenpak devkit
<DocScrutinizer05>
:-))
<azonenberg>
I made a little bridge that hooks some of the pins out to a PMOD
<azonenberg>
So i'm trying to measure delay down each wire to the zif socket
<azonenberg>
Goal is to allow measurement of pin-to-pin / internal propagation delays accurately
<azonenberg>
Without wire delay confounding the mix
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<azonenberg>
So after a bit of annoyance involving plugging my shorting jumper into the wrong row of the header...
<azonenberg>
I now have a loopback test from FPGA through the greenpak devkit header and back
<azonenberg>
next step, do some round trip latency measurements
<azonenberg>
Have to figure out the best way to do that...
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<azonenberg>
ooook i am going to have to scope this
<azonenberg>
this may be harder to characterize than i thought
<azonenberg>
Looks like some rework might be required
<azonenberg>
soo... the pins on the greenpak devkit have 100 ohm resistors on them for io protection
<azonenberg>
In both directions
<azonenberg>
The Zybo pmod has 200 ohm resistors on them
<azonenberg>
So all told I have 300 ohms from the FPGA to the greenpak, then another 300 going back
<azonenberg>
600 ohm round trip resistance plus all that wire capacitance, well... that certainly explains the 120 ns round-trip time i measured :p
<azonenberg>
I was using default drive strength, going higher miiight have helped, but i really have to get rid of those resistors
<azonenberg>
I don't like soldering to COTS devkits just in case i want to use them for something else, but... I don't see an alternative
<azonenberg>
my rise times are garbage
<azonenberg>
Hmm, there might be more to it? i might need to scope it
<azonenberg>
Guesstimating 20 pF of overall path capacitance we're looking at only a 12 ns tau
<azonenberg>
Which is off by an order of magnitude
<azonenberg>
There's still Rds(on) of the analog switches on the greenpak board but that isn't nearly so bad
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<azonenberg>
nats`: thought? I think i have some soldering to do
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<azonenberg>
But before i do that, scoping
<azonenberg>
Hmm interesting it looks like most of the delay may be on the greenpak board? i'm seeing ~3 clocks (24 ns) delay when i loop back on the pmod connector
<azonenberg>
and ~15 clocks (120 ns) when i loop through the greenpak
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<whitequark>
a long time ago I told a telco person, offhand, that his particular telco is "putrefying", and he's been enjoying that comparison ever since
<whitequark>
i think telco must be unhealthy for you
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