clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<corecode> hi
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<ZipCPU> Yo!
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<tpb> Title: A signed multiply verilog code using row adder tree multiplier and modified baugh-wooley algorithm · GitHub (at gist.github.com)
<daveshah> Implementing a full adder like that is going to give very poor results for FPGA synthesis
<promach_> daveshah: because of the topmost partial product layers ?
<promach_> wait, you were referring to full adder
<daveshah> Because FPGA synthesis tools are unlikely to infer carry logic from a full adder written as logic rather than +
<promach_> what do you mean by "rather than +" ?
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<daveshah> FPGA synthesis tools might not infer FPGA carry logic from AND/OR/XOR operators. They expect to see +/-/* operators to infer carries
<daveshah> I doubt performance will be good without using the fast carry chains
<promach_> daveshah: I see, this is the line cout <= (ain & bin) | (cin & (ain^bin));
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<daveshah> Yes, I don't know why you aren't just using the Verilog + operator
<daveshah> Unless this is for ASIC? Then it probably doesn't matter
<promach_> daveshah: cout <= (ain * bin) + (cin * (ain - bin));
<daveshah> You'd have to do it on a word
<promach_> ain, bin, cin, cout are of one bit
<daveshah> Yes, exactly, this is probably going to end up with a poor FPGA mapping
<daveshah> Just use a + b where a and b are words
<promach_> words ?
<daveshah> Multiple bits
<daveshah> A single-bit full adder module is almost always going to have poor FPGA results
<promach_> ok
<promach_> let me try both ways
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<promach_> Strange, I have multiple conflicting drivers warning for https://gist.github.com/promach/5f2d9a9494704ed93cf65687c982198c#file-multiply-v-L110-L113
<tpb> Title: A signed multiply verilog code using row adder tree multiplier and modified baugh-wooley algorithm · GitHub (at gist.github.com)
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