clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
<emeb> tnt: C compiler integrated into my repo -> https://github.com/emeb/icestick_6502
<tpb> Title: GitHub - emeb/icestick_6502: A small 6502 system build on a Lattice Icestick FPGA development board (at github.com)
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<emeb_mac> tnt: baby steps - got 6502 w/ cc65 working on a u4k
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<corecode> \o/ u4k
<corecode> i wonder how large that design is
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<tnt> \o/ https://pastebin.com/mTs9MwN7 Ok, so it still has quite a few issues and the sw side is a huge hack but ...
<tpb> Title: [16389700.930124] usb 1-2: new full-speed USB device number 71 using xhci_hcd [ - Pastebin.com (at pastebin.com)
<corecode> hi tnt
<tnt> hi.
<corecode> i'm debating implementing a HS USB SIE, so that i can skip the silly ftdi chips
<corecode> but maybe that's too much of NIH
<tnt> well, for the ice40 I think this would take up way too much space to be relly useful.
<corecode> yes
<corecode> although - you think HS would take much more space than FS?
<tnt> There are some ARM with HS that really don't cost a lot more than they phy.
<corecode> yea the cheapest i found are the sam3u
<sorear> Have you looked at valentyusb and the tinyfpga boards?
<tnt> corecode: we were looking at nuc505dl13y which is 2$
<tnt> sorear: what's your point ?
<corecode> who sells the nuc?
<sorear> tnt: tinyfpga did exactly what corecode is asking about -bitbang USB (forget which speed) on ice40 to avoid the footprint of a separate ftdi
<tnt> sorear: no, he's talking about HS ... 480mbps, you need a phy.
<tnt> corecode: nuovoton directly.
<corecode> good, they had some availability issues
<corecode> uh wow that is a nice chip at that price
<corecode> ah, embedded spi flash, interesting
<corecode> thanks, that's a good lead
<corecode> how did you find them?
<tpb> Title: Explore options for FTDI replacement · Issue #14 · icebreaker-fpga/icebreaker · GitHub (at github.com)
<corecode> ah, samg as well
<corecode> ah no
<corecode> classic usb confusion
<corecode> tnt: thanks, that's a great find
<corecode> now the question is, can it do a fast bidirectional bus
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<corecode> i've used nuvoton chips some years ago
<corecode> took me a while to get the usb peripheral going back then
<corecode> hm, doesn't look like there is any kind of bus mode
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<tnt> corecode: SD Host is probably the best it can do.
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<corecode> tnt: seems like a roundabout way to transmit data. what do you think?
<tnt> corecode: well it's not ideal, but that's probably the highest bandwidt peripheral on there.
<tnt> It's basically a quad SPI port.
<corecode> and i guess DDR
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<shapr> Does this mean vmware/cascade would work better on a BeagleWire? https://github.com/vmware/cascade/issues/83#issuecomment-469389807
<tpb> Title: support for yosys backend? (or fill out "adding new backends" docs section?) · Issue #83 · vmware/cascade · GitHub (at github.com)
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<emeb> tnt: here's the 6502 project ported to a up5k -> https://github.com/emeb/up5k_6502
<tpb> Title: GitHub - emeb/up5k_6502: A simple 6502 system built on a Lattice Ultra Plus 5k FPGA (at github.com)
<emeb> I tweaked it slightly to use one of the SPRAM cores for the main system memory, so the 6502 has 32kB RAM and 4kB ROM in this build.
<tnt> emeb: nice ! I'll try to give this a shot next week end :)
<tnt> emeb: what target board did you use btw ?
<emeb> tnt: I built it on a upduino I had laying around.
<emeb> and I used my custom-made USB->SPI board to directly load the up5k so you'll definitely need to tweak the "make prog" target for whatever programming hardware you have.
<tnt> I'll probably try on the icebreaker and use iceprog.
<emeb> tnt: great - I was hoping someone would try it on that. I don't have one so I can't do it myself.
<emeb> does icebreaker have a USB serial port hooked up to the FPGA?
<tnt> yes it does.
<tnt> the same ftdi that's used for programming has a 2nd interface configured as uart.
<emeb> nice. so pretty much all you need to do is rearrange the pin assignments in the .pcf file to match the icebreaker I/O.
<emeb> and revise the 'prog' target in the makefile.
<tnt> I might try it tonigh. Depends how long it takes me to cleanup the microcode from my usb core :)
<emeb> cool - let me know if you run into any snags I could help with.
<tnt> Is there a demo app btw ? (didn't look really deep yet)
<tnt> how is it loaded in spram ?
<emeb> There is demo code but it's preloaded into a ROM that's implemented w/ EBR.
<corecode> how big is the cpu design?
<emeb> you mean how much of the FPGA does the whole thing use?
<emeb> here's the nextprn resource table: https://pastebin.com/eVVZnwnP
<tpb> Title: Info: Device utilisation: Info: ICESTORM_LC: 1043/ 5280 19% Info - Pastebin.com (at pastebin.com)
<corecode> nice
<emeb> plenty of logic left over
<corecode> makes me feel like my cpu design isn't too bad
<emeb> yours is smaller?
<corecode> yes, around 600
<corecode> and it is a 16 bit cpu
<emeb> kewl
<tnt> corecode: nice, that's about the size of my 16b cpu as well. Hard to go smaller.
<corecode> yea, the alu mux makes it quite big
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<emeb> hmmm... something weird going on with the ACIA. Works OK for TX but reading RX data isn't clearing the IRQ as it did in my other designs. grmbl.
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<emeb> fixed & pushed
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