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<rrika>
hi, I just want to confirm something, I had a verilog array of size "[3:0] name [0:2047]" with one write (name[a] <= ...), and two reads ({name[b], name[b+1]}) which didn't end up using my ecp5's ram
<rrika>
it did however use them when doing only one read ({name[b], name[b]})
<rrika>
so is that because of the number of read ports?
<daveshah>
Yosys can create more read ports by duplicating the BRAM
<rrika>
automatically or on explicit instruction, in this case splitting suffices
<daveshah>
However, a separate <= for each read port is probably required
<rrika>
ah, I wrote b and b+1 but really it was {b, 1'b0} and {b, 1'b1}, so it's really clear they never alias
<rrika>
daveshah, an assign is not good enough?
<daveshah>
I think the concatenation might be the problem
<daveshah>
Something like x[3:0] <= name[b]; x[7:4] <= name[b+1]; should work
<daveshah>
Yosys needs to merge a DFF into the read port to map sync BRAM
<daveshah>
With the concatenation, a single 8-bit DFF is created and I don't know if it can split that. With the two assigns, two 4-bit DFFs will be created that should merge fine
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<rrika>
daveshah, that would still mean though that the contents are duplicated, right?
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<daveshah>
Yes, Yosys doesn't support mixed read/write widths which would be the most efficient solution
<daveshah>
The other possible solution would be to use one of the two ports of the BRAM as both read and write if read and write are exclusive, but Yosys doesn't support this either
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<tnt>
mmm ... having a long flatten wire x[(32*N)-1:0] representing N wires of 32 bits, how would you 'OR' them all together ? (for any N)
<emeb>
wire flat = |x; ?
<tnt>
well ... no ... I want a vector of 32 bits at the end.
<tnt>
every i-th bit of each of the N vector ORed together.
<emeb>
ah - or in only one dimension
<emeb>
sounds like a good excuse to use a for loop
<tnt>
yeah, but my attempts to do so, haven't resulted in anything I can build :/
<tnt>
err ... I swapped +: and :+ :/
<emeb>
pebkac :)
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