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<MoeIcenowy>
sorry to ask icarus verilog question here
<MoeIcenowy>
is there a way to access a submodule in the top module without knowing the name of the top module?
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<tnt>
Finally took the time to write custom pass for yosys to init BRAM from a file ... https://github.com/YosysHQ/yosys/pull/859 much better than my hacked python script modifying the json between yosys and nextpnr :p
<tpb>
Title: iCE40 BRAM primitives init from file by smunaut · Pull Request #859 · YosysHQ/yosys · GitHub (at github.com)
<emeb_mac>
is there any way to insert BRAM init *after* nextpnr?
<tnt>
Well, there is icebram but that requires the BRAM to be initialized with known random value during synthesis
<tnt>
and then it finds those in the bitstream and replaces them.
<tnt>
(so you synth with a initfile of random value and you save that random.hex, then after nextpnr you can use icebram and give it both random.hex and real.hex and it will find those bram in the bitstream and replace their content).
<emeb_mac>
interesting approach.
<emeb_mac>
sounds like they didn't know where in the bitstream the init data would end up so they had to search for it?
<emeb_mac>
which doesn't make much sense given that the entire toolchain is FOSS at this point.
<tnt>
Well yeah, because (1) it's used also for inferred RAM where you have no idea how the structure of the RAM is vs actual physical BRAM (2) nextpnr doesn't really save any mapping on which 'ram' ends up where.
<emeb_mac>
ok, that makes sense.
<corecode>
tnt: oh you're sylvain!
<corecode>
we met at 35c3
<corecode>
i asked you about the led panel refresh
<tnt>
I am. and you did ? Well a lot of people asked about it so you'll have to be a bit more precise :p
<corecode>
hah
<corecode>
i was sitting at the table for a couple of days, working on my fpga board (u4k :)
<tnt>
Oh yeah, I remember that !
<corecode>
hi
<tnt>
You went through quite a bit of trouble to get that board supported :)
<corecode>
yea and it was user error even
<corecode>
turned out to be a bad icecube config - redid it and then the cpu design linked
<corecode>
heh oh well
<tnt>
What are the u4k advantage over the up5k ?
<corecode>
i have them here :)
<corecode>
also, cheaper
<emeb_mac>
heh
<corecode>
i might go use ecp5 for future projects, they seem to be quite cheap as well, especially for what they have
<tnt>
They're a whoile lot trickier to solder though.
<corecode>
i think 0.8mm bga will be fine
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<emeb_mac>
also hard to break out the pads on std PCB processes
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<corecode>
i'll have to look into that
<corecode>
but i do 4 layers anyhow
<emeb_mac>
unless you use tricks like tinyfpga does where he allows pads to short together & lose I/O count
<corecode>
uh no
<corecode>
no hax
<corecode>
i think it should be fine
<corecode>
if you break out diagonally
<emeb_mac>
they look like nice parts though - lots of resources.