<sxpert>
now, to debug what next_pnr states is "ERROR: timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc."
<daveshah>
sxpert: what happens if you grep the Yosys output for DLATCH?
<tpb>
Title: Problem with seeing internal generate variable and coverage failed issue with signed multiplication verilog code - Stack Overflow (at stackoverflow.com)
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<ZipCPU>
promach_: The tools are open source. The standard is on line. The VCD format is public/published. Why not dig into the problem and figure out what's going on for yourself?
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<sxpert>
daveshah: there, all fixed (after a good night sleep)
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<promach_>
ZipCPU : I have made cover(in_valid) passed