clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<ZipCPU> xerpi: The github issue has been closed, although I haven't tried the updated version myself (yet)
<ZipCPU> mithro: I didn't get your comment on the issue tracker. Care to explain what's so awesome about ABC moving?
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<cr1901_modern> ZipCPU: It means I don't have to deal with Mercurial anymore :)
<ZipCPU> Ahh ... okay. That wasn't clear from your post ... :)
<cr1901_modern> ZipCPU: My personal opinion does not necessarily reflect mithro's :)
<ZipCPU> Ahm ... okay ... Sorry.
* cr1901_modern told a bad joke :(
<ZipCPU> Well ... not that so much as ... you've left me confused.
<ZipCPU> When you answered for mithro, I assumed that cr1901_modern and mithro were two pseudoname's for the same person, so I responded as such
<ZipCPU> No I feel embarrassed for having made a mistake
<cr1901_modern> Nah, I am not mithro :). Tim's Australian, I'm... well, from NJ
<ZipCPU> Ah, ok
<ZipCPU> I guess I was just confused.
<ZipCPU> It's nearly nighttime in here on the East coast, so ... I'm doing my vesper's and thinking about testing a SPI flash simulator before bed ...
<cr1901_modern> What is a vesper?
* ZipCPU checks the dictionary ...
<ZipCPU> Vesper: evening prayers
<cr1901_modern> Ahhh I see
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<promach> Just for curiousity, what do you guys think about https://i.imgur.com/JDrAIL0.png ?
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* shapr hops quietly
* ZipCPU wonders if shapr likes "hip hop"
<shapr> well, I like hop
<shapr> howdy ZipCPU! How you doin?
<ZipCPU> Frustrated.
<ZipCPU> I spent all yesterday trying to figure out how to reconfigure a Cyclone-V FPGA.
<shapr> that does sound frustrating
<ZipCPU> The interface that's well documented no longer exists, and Linux doesn't like my attempts at building device tree overlays
<ZipCPU> (I've never built them before, so ... this is a new thing for me as well.)
<shapr> new things are good
<ZipCPU> While device tree overlays are the wave of the future for reconfiguring FPGA's without taking the O/S down, Linux didn't accept any of my attempts. As a result, I'm fruitless searching the Linux kernel for clues as to what I'm doing wrong.
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<shapr> sadly, I know nothing about that
<ZipCPU> Lol ... yeah, that's my problem: neither do I :P
<shapr> did you ask on twitter?
<shapr> lots of FPGA people connected to you
<shapr> that's what I do when I'm stuck on a problem
<ZipCPU> No. I complained on twitter.
<shapr> I got a good answer when asking whether murmurhash3 or siphash was better for a bloom filter.
<daveshah> Must say it's a lot easier on a Zynq, you just `cat` the new bitstream into a device node
<ZipCPU> You mean like, cat configuration.bin > /dev/fpga0 ?
<ZipCPU> That interface has been deprecated in the Linux kernel, and that's part of what I'm struggling with.
<awygle> DTOs are awesome but they're pretty new, do you have a recent kernel? 4.x?
<daveshah> Yes, that's how I did it when I was doing Zynq stuff. Didn't know it had been deprecated. Have always found device tree stuff a bit of a pain tbh
<shapr> what's better about the device tree?
<ZipCPU> Well ... the idea is that the device tree captures some of the dependencies required by loading
<ZipCPU> For the Cyclone-V part, you need to turn off the bus "bridges" to the FPGA before you can reload the configuration
<ZipCPU> And the device tree is supposed to help encapsulate that process
<awygle> device trees are a great idea - describe the PCB to the kernel so it knows what's physically attached - but yes the implementation is a bit hair-pulling
<ZipCPU> Especially when it's not well documented.
<shapr> oh, the tree describes what devices are attached to what?
<ZipCPU> So, a bit of history ...
<awygle> i find that Beaglebone has the best documentation for this kind of thing, or did ~1yr ago
<ZipCPU> Device trees were invented primarily because of ARM. ARM was selling a CPU in terms of IP, and every chip maker was adding their own devices to it
<ZipCPU> To deal with this, Linus invented the device tree--something that tells Linux what devices are available to it and where they are found in the memory map
<daveshah> In general my problem hasn't been the device tree system itself, but the vendor documentation for it
<daveshah> I agree in theory it is a good idea
<ZipCPU> daveshah: What, you've struggled with this as well?
<shapr> ZipCPU: sounds good so far
<daveshah> Various previous projects, mostly doing slightly weird stuff on a Zynq
<q3k> and before DT we had ARM machine/board IDs
<q3k> *shudder*
<awygle> device trees would be easier to use if they were attached to better subsystems.... ;)
<daveshah> I remember a project I did with the iMX233 using 2.6
<ZipCPU> shapr: So, the next step was a "device tree overlay". This was supposed to support hardware reconfiguration
<daveshah> With a hardcoded C file doing init
<awygle> i tried to do GPIO stuff recently, that got _complicated_
<ZipCPU> With a device tree overlay, you can "add hardware" to running Linux system, and keep the kernel informed of what's there.
<shapr> sounds useful?
<q3k> daveshah: did that for some OMAPs, that was, uh, fun
<ZipCPU> shapr: However, the overlay must match the current kernel in enough detail in order to be understood. That's where I seem to be failing.
<q3k> and then there's some vendors (*cough* allwinner *cough*) that ship their own clone of DT because why not
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<mjo-uk_> I think it's the case that not all device tree subsystems support loading stuff dynamically. I hit this problem about a year ago trying to reconfigure the LED subsystem on a Raspberry Pi. So it works if you load it at boot but you can't unload it and load it again on a live system.
<ZipCPU> mjo-uk_: Thanks for the insight. This might be my problem.
<mjo-uk_> ZipCPU: A pleasure. By the way, I've really enjoyed reading your many fine articles about FPGA design. Thank you so much for posting them.
<ZipCPU> Thank you!
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<mattvenn> just continuing on this DTO thread, recent beaglebone stuff has done away with the dynamic loading of overlays
<mattvenn> it's never worked properly - have to set it up at boot
<mattvenn> there are some very useful people on the #beagle channel
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<janrinze> hi people here
<sorear> hi
<janrinze> are there people here who are willing to teach me some tricks on timing analysys?
<janrinze> hi sorear
<awygle> janrinze: unless you are specifically talking about "icetime", i suspect this will not be the most productive channel for you, you may wish to try ##fpga
<janrinze> icetime indeed
<janrinze> I'm not yet familiar with what it can do for me to find slowest path and such
<janrinze> 36.556 ns .. 37.145 ns $abc$54082$n2094_1
<janrinze> 37.461 ns .. 38.050 ns $abc$54082$n2085_1
<janrinze> this kind of feedback is hard to trace back to something in the verilog.
<janrinze> 41.108 ns .. 44.657 ns $abc$54082$n3465_1
<janrinze> 38.450 ns .. 40.729 ns $abc$54082$n2147_1
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<awygle> ah, yes. that's a known problem with abc eating net names...
<awygle> one moment, i have something for you to try...
<awygle> so there's an ABC command called "dress" which supposedly can recover some net names
<awygle> i'm not entirely sure how to use it but it looks like you need a pre-synthesis netlist for comparison
<awygle> so i guess you'd give "abc dress" your pre-synthesis and post-par netlists, it would recover names in the post-par list, then you'd run icetime on that?
<janrinze> just add 'dress' to abc? (I use abc2)
<janrinze> yosys -p 'synth_ice40 -abc2 -top top -blif $@' $<
<janrinze> should become
<janrinze> yosys -p 'synth_ice40 -abc2 dress -top top -blif $@' $<
<janrinze> is that correct?
<janrinze> I was assuming there should be some kind of config for abc that I need to change
<awygle> i think you might need to call dress from abc directly rather than through yosys, but i'm not sure
<janrinze> the documentation is not quite clear on how to add abc flags in yosys
<awygle> i have not actually tried the dress command so you'd be charting new territory :) you might get better names out of icetime if you pass -noabc instead of -abc2, but you'll get worse results as well, so probably not helpful if you're trying to figure out why you're not meeting timing
<janrinze> yes.. abc2 yields best result for my design. switching that off surely will generate a lot worse timings, i agree
<janrinze> synth_ice40 seems to be a reference to a script but i cannot find it. it is probably compiled-in in yosys.
<tpb> Title: Yosys Open SYnthesis Suite :: Command Reference :: synth_ice40 (at www.clifford.at)
<janrinze> that is exactly the page i am looking through.
<awygle> it's basically just a shortcut for a bunch of other commands
<awygle> rqou: did you actually try "dress"?
<awygle> rqou: slash, do you know any other tricks to help janrinze?
<janrinze> ERROR: Command syntax error: Unexpected option in selection arguments.
<janrinze> i copied the commands from the documentation and put them into a script for yosys. Unchanged it works okay.
<janrinze> when i add 'dress' to abc , yosys still works but arachne-pnr is not happy anymore..
<janrinze> fatal error: invalid .names entry: both gates must be 1 here
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