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<ZipCPU>
Hey, this is cool! Building an RGMII network interface. Last time I did this, I had to iterate over many painful rounds with the simulator. This time, I think I got it right with less than one bug found in the network code.
<ZipCPU>
(Other bugs were found in the bus addressing, etc.)
<ZipCPU>
The difference? This time I formally proved all of th network sub-components: add a CRC, add a hardware MAC, add a preamble, insure a minimum packet length, and then the inverse on the receive.
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<awygle>
ZipCPU: nice!
<ZipCPU>
;) The last time it was an RMII interface, but still ... I had to rebuild the whole thing to operate on 8-bits at a time instead of 4.
<awygle>
my actual job has been throttled to 11, i look forward to getting back to personal projects...
<awygle>
i think i've come up with a way to prove the fifo that i find aesthetically superior to breaking out the internal pointers
<ZipCPU>
Yeah, I understand comppletely about the job.
<ZipCPU>
As for the FIFO, I'd love to see it ... but I'll be glad to wait until you either get it working or get stuck.
<awygle>
i'll be sure to show you when i get there :)
<awygle>
it may be somewhat ridiculous to stress out over these kinds of things, but i'm much more interested in developing an approach than a formally verified fifo in particular
<awygle>
can you share anything about the project which has you developing an RGMII core?
<ZipCPU>
Sure! Most of the code is on line at https://github.com/ZipCPU/videozip although I haven't yet checked in all of the ethernet components.
<tpb>
Title: GitHub - ZipCPU/videozip: A ZipCPU SoC for the Nexys Video board supporting video functionality (at github.com)
<tpb>
Title: GitHub - ZipCPU/openarty: An Open Source configuration of the Arty platform (at github.com)
<ZipCPU>
Only thing is .... they need to be modified from RMII to RGMII, and I took the opportunity to add formal proofs along the way.
<ZipCPU>
(To be posted ...)
<awygle>
very interesting! thanks
<awygle>
(this bot is kind of weird thoughj)
<ZipCPU>
Yeah .... not sure I like it.
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<mattvenn_>
I got my i2c master workiong with the new sensor
<mattvenn_>
I made 3 changes: repeated starts, more setup/hold time consideration and learnt something new that was really important
<mattvenn_>
master shoudl nack the slave on the last data packet when reading
<mattvenn_>
it's in the spec but it hadn't mattered on previous sensors. This one actually followed the spec and kept the sda line down without the final nack from the master
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