clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<awygle> promach_: i wanted to make sure that parity and frame errors would be detected. otherwise i'd still pass verification even if i just said "assign frame_error_o = 1'b0".
<promach_> awygle: but how are you going to pass verification if you do cover(error) ?
<awygle> "cover" is like the opposite of BMC - if it's possible to reach the state, you pass. So you can do both cover(success) and cover(error) and satisfy both conditions
<awygle> (with two different traces of course)
<awygle> Try it and see - it will produce an example trace for 'valid', one for 'frame error' and one for 'parity error'
<promach_> ok, awygle: I will do cover(error) as well then
<promach_> so, what do you plan to do with the example trace for cover(error) ?
<awygle> promach_: nothing, really. it's just an existence proof. the assert()s say "if a parity error is detected, it is detected correctly". the cover() says "a parity error can be detected".
<awygle> you need both halves to really have confidence in what you're doing
<awygle> does that make sense?
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<promach_> awygle: I need to think a bit about what you just said. existence proof for an example parity error trace ... means UART could have parity error ? that does not really give me confidence :(
<awygle> promach_: it means that _if_ your UART _sees_ a parity error (from some other guy who wrote his UART transmitter half-drunk), it will _detect_ that parity error
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<promach_> ok, haha. I see
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