clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<nikhilp> hello
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<ZipCPU> nikhilp: Please stick around next time, we like to chat but ... sometimes you need to wait a while for a response.
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<philtor> So there's a bridge between GHDL and Yosys now?
<tpb> Title: GitHub - tgingold/ghdlsynth-beta: VHDL synthesis (based on ghdl) (at github.com)
<philtor> a VHDL frontend?
<philtor> requires a patch to yosys source
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<ZipCPU> philtor: I know there's a vhdl2verilog front end to yosys, I just don't know how well it works
<philtor> This ghdlsynth looks like it would be a better path - GHDL's VHDL parser is pretty mature
<philtor> Obviously, it's very beta at this point
<philtor> However, it requires patching yosys source and likely the source has gotten out of sync with that patch by now
<awygle> Yes, that's very exciting
<philtor> The patch is fairly small, though.
* ZipCPU just doesn't get all that excited about VHDL tools ... ;P
<awygle> GHDL is GPL though, as pointed out on another channel. I wonder how that works.
<philtor> tgingold should do a pull request to YosysHQ for that patch
<awygle> ZipCPU: I'm excited for someone to give me a reason to learn VHDL!
<ZipCPU> Run away!
<ZipCPU> Fast!
<daveshah> It looks like it can also be loaded as a dynamic library without needing a patch
<daveshah> But I haven't investigated much
<philtor> Yes, but a patch is requireed to support that
<philtor> so I don't think licensing should be an issue
<philtor> In fact, the patch appears to only be to the yosys Makefile
<philtor> yes, that seems to be the only thing being patched.
<philtor> Good separation between the two projects
<philtor> no licencing issues
<philtor> looks a lot like the verific bridge
<philtor> Pretty cool, but needs work.
<philtor> Fortunately, the only code in the bridge is in C++
<philtor> so you don't need to learn Ada
<philtor> to contribute
<daveshah> Looks like the dynamic library does work without the patch using the Yosys module system - but I agree the patch is a much nicer approach
<daveshah> AFAIK a lot of the work is being done by the `synth` part of ghdl which is in Ada, I don't know how complete that bit is
<tpb> Title: ghdl/src/synth at master · ghdl/ghdl · GitHub (at github.com)
<philtor> ah, right. It's actually in the GHDL codebase already.
* shapr hops cheerfully
<shapr> vacation is GREAT!
<ZipCPU> At the last robotics competition, they asked what a robot's favorite type of music. The FROGbots team replied "Hip hop", although the answer for all the other robots was "Heavy metal"
<shapr> bwahahaha
<shapr> ZipCPU: twitter worthy for sure
<ZipCPU> Here's a question for those with experience using the concurrent assertions that yosys (without verific) doesn't (yet) support ...
<ZipCPU> What's the "killer app" that makes such assertions valuable?
<ZipCPU> What's the "killer app" that makes such *concurrent* assertions valuable?
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<ZipCPU> Hmm ... assertions for a UART: 117 lines without concurrent assertions, 47 lines with ...
<ZipCPU> ... wonder what the difference would be for a SPI flash ... ?
<sorear> can concurrent assertions always be replaced with regular assertions?
<awygle> ZipCPU: all i want in the world is for a notion of a "property" as a first class object
<ZipCPU> sorear: I think the right way to answer your question would be to start with: there are two types of assertions (or assumptions) concurrent and immediate.
<ZipCPU> yosys currently only supports the immediate assumptions.
<ZipCPU> concurrent assumptions include the System Verilog sequence/property language subset.
<cr1901_modern> ? "assert property" is a concurrent assertion.
<cr1901_modern> yosys supports that, it just doesn't support anything else :P
<awygle> yosys only supports that in a trivial way, and does so by converting it to the implied immediate version, iirc
<cr1901_modern> http://www.clifford.at/papers/2016/yosys-smtbmc/slides.pdf slide 11, awygle is correct. And I even read this presentation multiple times :(
<ZipCPU> cr1901_modern: Yosys does not support: assert property (A |-> B ##1 C [*3:8] ##1 !B); as an example.
* awygle prints out "awygle is correct", frames it, adds it to a wall of dozens of similar frames
<cr1901_modern> Well idk if yosys supports ##, but it certainly doesn't support |->
<cr1901_modern> last I checked*
<awygle> i just want to be able to do "assert property(acks_are_happy)" and define what happiness means to acks somewhere else
* ZipCPU signs awygle's printout
<tpb> Title: system verilog - SystemVerilog: implies operator vs. |-> - Stack Overflow (at stackoverflow.com)
<awygle> otherwise it feels like an SLA principle violation
<awygle> but it's possible i could solve this problem with functions if i knew verilog better
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