sb0 changed the topic of #m-labs to: https://m-labs.hk :: Mattermost https://chat.m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<sb0> whitequark: do you have any recommendations on how to stream logic analyzer data from one of those Saleae devices (https://sigrok.org/wiki/Saleae_Logic) into python?
<whitequark> sb0: well... sigrok? it has python bindings iirc
<sb0> I want a continuous stream of data (analyzer continuously sampling without glitches), ideally passed into numpy arrays some thousands samples deep
<sb0> okay and that sigrok lib works correctly? have you tried it? i saw you reimplemented many things yourself in glasgow...
<whitequark> glasgow is orthogonal to sigrok though, no?
<whitequark> it pays off to reimplement things in glasgow because i can use python to share code between gateware and software, so i don't have to e.g. add some complicated serialization to explain sigrok what channels, sample rates, etc I need. also sigrok doesn't work well with glasgow's internal logic analyzer because it doesn't support multibit signals
<whitequark> and glasgow's LA shows you FIFO reads and writes
<sb0> ok
<whitequark> anyway, i didn't try that part of sigrok's python bindings myself
<whitequark> i only really wrote decoders for it
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<whitequark> I suppose you could also use sigrok-cli to stream data into an unix FIFO in straight binary, or something like that
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<mtrbot-ml> [mattermost] <sb10q> Hmm I'll see. For that FIFO approach, Python I/O seems a bit slow, and I need at least 5Msps on 3 channels
<mtrbot-ml> [mattermost] <sb10q> Something that writes numpy arrays directly and efficiently sounds safer
<whitequark> 15 MB/s?
<whitequark> I easily hit 30 MB/s with Python, libusb, and glasgow
<whitequark> and that's without any numpy arrays, just regular Python memoryview, and some pretty crappy code too
<whitequark> s/30/40/, actually
<whitequark> wait, no, 3 channels fit into 1 byte, so it'd be just 5 MB/s
<whitequark> that's completely trivial
<mtrbot-ml> [mattermost] <sb10q> Well OK, but you need to separate them afterwards
<mtrbot-ml> [mattermost] <sb10q> Anyway I can benchmark that easily
<whitequark> sure, use numpy for that
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<sb0> okay, this sigrok stuff just works out of the box. nice!
<sb0> no firmware to compile, fxload, etc.
<whitequark> yes, sigrok is quite good. unfortunately it is badly understaffed.
<whitequark> the core needs some significant refactoring to really get to its full potential and there's not enough people working on it
<whitequark> e.g. pulseview ought to be better than gtkwave. and decoders should not choke on 100Ms of mostly idle data points.
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<_whitenotifier-3> [nmigen] whitequark opened issue #160: pysim is very slow - https://git.io/fjDdl
<_whitenotifier-3> [nmigen] whitequark opened issue #161: pysim should have a way to reset user/sync signals - https://git.io/fjDd8
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<isengaara-tomoko> When using NMigen I get UnusedElaboratable warnings, meaning that
<isengaara-tomoko> class Fragment: @staticmethod def get(obj, platform): while True: if isinstance(obj, Fragment): return obj elif isinstance(obj, Elaboratable): obj._Elaboratable__used = True
<isengaara-tomoko> is never called
<whitequark> indeed. any elaboratables that are created but not synthesized display this message
<isengaara-tomoko> so I just need to connect each Elaboratables output
<isengaara-tomoko> I currently working on a unittest for a TLB, and all inner modules have already been tested
<whitequark> are you adding the modules that show UnusedElaboratable warning as submodules somewhere?
<whitequark> that's the bug this warning is supposed to guard against
<isengaara-tomoko> I think yes, the modules are added as submodules
<isengaara-tomoko> however the code was generated using a systemverilog to nmigen converter and had to be modified manually to run inside nmigen
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<cr1901_modern> sb0: I sent a privmsg and email when you get the chance.
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