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[nmigen] whitequark opened issue #147: Reduce-op (reduce-or, reduce-and, reduce-xor) -
https://git.io/fjXCK
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[nmigen] whitequark opened issue #148: Operator like .part() that returns a non-overlapping chunk of signal -
https://git.io/fjXCx
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[nmigen] whitequark commented on issue #147: Reduce-op (reduce-or, reduce-and, reduce-xor) -
https://git.io/fjXWf
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[nmigen] whitequark commented on issue #98: Generated Verilog should be more readable -
https://git.io/fjXWG
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[nmigen] sbourdeauducq commented on issue #147: Reduce-op (reduce-or, reduce-and, reduce-xor) -
https://git.io/fjX4f
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[nmigen] whitequark commented on issue #147: Reduce-op (reduce-or, reduce-and, reduce-xor) -
https://git.io/fjX4t
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[nmigen] zignig commented on issue #108: Simulations for code that uses Platform -
https://git.io/fjX4Y
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[nmigen] cr1901 opened pull request #149: build.run: Ensure batch script returns proper error code. -
https://git.io/fjXu7
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[nmigen] codecov[bot] commented on pull request #149: build.run: Ensure batch script returns proper error code. -
https://git.io/fjXuA
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[m-labs/nmigen] cr1901 b963449 - build.run: Ensure batch script returns proper error code.
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[nmigen] whitequark closed pull request #149: build.run: Ensure batch script returns proper error code. -
https://git.io/fjXu7
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[nmigen] Fatsie opened pull request #150: Pin: Add extra hierarchy level for name derivation -
https://git.io/fjXzQ
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[nmigen] codecov[bot] commented on pull request #150: Pin: Add extra hierarchy level for name derivation -
https://git.io/fjXz7
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[nmigen] whitequark closed pull request #150: Pin: Add extra hierarchy level for name derivation -
https://git.io/fjXzQ
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[m-labs/nmigen] Fatsie ff343d5 - Pin: Add extra hierarchy level for name derivation
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[nmigen] andresdemski opened issue #151: Question: How to change FIFO clock dommains? -
https://git.io/fjXgb
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[nmigen] peteut commented on issue #151: Question: How to change FIFO clock dommains? -
https://git.io/fjXgj
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