<sb0>
rjo, what exactly is "f,p,a,u modulation by RTIO (eDRTIO) for all interpolators" and "Coherent phase mode (implemented in kernel API and runtime) for frequency/phase updates of the three eDRTIO channels"?
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<rjo>
that was explained in the overall design doc that we wrote last year.
<rjo>
both were.
<rjo>
it started in joe's draft_sayma_metlino_procurement_20160805.pdf
<rjo>
mntng: do you feel up to tackling #799 yourself?
<sb0>
rjo, another gotcha with the SPI implementation is, when you're doing a 8-bit transfer you must do write(0x**000000) instead of simply write(0x**)
<GitHub55>
[artiq] sbourdeauducq commented on issue #800: Are we programming the FTDI chip? I recommend we don't, or only with existing software that is already proven to "work" with their buggy silicon. https://github.com/m-labs/artiq/issues/800#issuecomment-316754706
<GitHub29>
[artiq] jordens commented on issue #800: Right. But IIRC there needs to be some programming to tell the chip how to use and expose the four ports. Maybe that's also something that the manufacturer can do. https://github.com/m-labs/artiq/issues/800#issuecomment-316766184
<GitHub188>
[artiq] sbourdeauducq commented on issue #800: Doesn't OpenOCD reconfigure them dynamically? IIRC the only benefits of EEPROM programming are 1) the JTAG port won't appear as a ttyUSB device before OpenOCD claims it 2) fancy USB identifiers. https://github.com/m-labs/artiq/issues/800#issuecomment-316767154
<GitHub138>
[artiq] jordens commented on issue #800: IIRC the serial port doesn't appear at all. That needs eeprom programming. Nothing in the current openocd code even touches that. Maybe the JTAG port doesn't need an EEPROM. But that kills one way of distinguishing Saymas. https://github.com/m-labs/artiq/issues/800#issuecomment-316779795
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<cr1901>
Would still like to see a full CPU in Migen someday, but that looks like a decent RISCV impl from a quick glance