02:49 <GitHub121> [artiq] sbourdeauducq commented on issue #767: You need to connect the computer that runs artiq_flash to the micro-USB port of the kc705. Note that the kc705 has several USB ports and you must use the one with JTAG. Is the JTAG device recognized in dmesg and lsusb? HDMI is not used anywhere. https://github.com/m-labs/artiq/issues/767#issuecomment-312405992

04:48 <GitHub115> [artiq] sbourdeauducq opened issue #768: inappropriate error message when using integer constant as boolean https://github.com/m-labs/artiq/issues/768

07:03 <sb0> _florent_, did you receive the sayma boards?

07:36 <_florent_> sb0: no, I was not there yesterday but I don't have any notification and tnt tracking isn't updated...

07:38 <sb0> sigh

09:56 <key2> sb0: what do you think of a rtl simulator based on openCL ?

09:57 <key2> sb0: I was thinking one could synth a verilog code with yosys for example, and generate the proper kernel for openCL in order to get it simulated faster than with verilator or other

11:27 <sb0> how does yosys help?

11:28 <sb0> opencl is a cpu-style environment, yosys will give you a netlist

11:29 <whitequark> is FPGA simulation even parallelizable to SIMD hardware?

11:29 <whitequark> well, gateware simulation

11:30 <sb0> if you like GPUs, iirc LLVM can target some of them

11:31 <sb0> maybe you could compile migen into gpu code using a llvm python binding

11:31 <sb0> (migen is also much simpler to deal with than verilog)

11:32 <sb0> but of course if you call python at every cycle to transfer data then it'll probably slow things down

13:02 <whitequark> looks like people do simulate logic on GPUs http://on-demand.gputechconf.com/gtc/2012/presentations/S0050-High-Performance-Logic-Sims-with-GPUs.pdf

13:02 <whitequark> using CUDA, so not even any LLVM needed

13:06 <cr1901_modern> How might you simulate it in LLVM anyway (there's lots of "spooky action at a distance" in HDL)?

13:07 <cr1901_modern> Should prob take a look at how verilator does it

13:19 <sb0> "spooky action at a distance" in HDL?

13:21 <cr1901_modern> sb0: you set one variable (reg) and it will automatically affect the value of all variables (wires) dependent on the first one.

13:21 <cr1901_modern> I've heard it compared to FRP, but Idk enough about that type of programming to comment

13:21 <sb0> you can have the same thing reg to reg; the wire/reg distinction in verilog has no basis

13:24 <cr1901_modern> fair enough; was just an example

14:52 <whitequark> cr1901_modern: well you don't simulate it directly

14:52 <whitequark> you preprocess it into some different representation

14:53 <whitequark> if there are no logic loops then a single warp could be handling a single flip-flop or something

14:53 <whitequark> not a lot of data locality but at least it parallelizes

17:34 <GitHub167> [artiq] jbqubit opened issue #769: ad9154 bad CODEGRPSYNCFLG https://github.com/m-labs/artiq/issues/769

17:59 <GitHub78> [artiq] jbqubit opened issue #770: phaser: 55 seconds to load demo_2tone.py https://github.com/m-labs/artiq/issues/770

18:11 <GitHub28> [artiq] sbourdeauducq commented on issue #769: Details? Obviously it doesn't do that every time. https://github.com/m-labs/artiq/issues/769#issuecomment-312447336

18:13 <GitHub194> [artiq] sbourdeauducq commented on issue #770: Likely not a problem with the latest version. https://github.com/m-labs/artiq/issues/770#issuecomment-312447429

18:13 <GitHub109> [artiq] sbourdeauducq closed issue #770: phaser: 55 seconds to load demo_2tone.py https://github.com/m-labs/artiq/issues/770

18:14 <GitHub193> [artiq] sbourdeauducq commented on issue #770: That one you are reporting about is before a lot of TCP fixes. https://github.com/m-labs/artiq/issues/770#issuecomment-312447502

18:16 <GitHub170> [artiq] jbqubit commented on issue #770: Sure. I can believe this got better with TCP fixes. In light of #769 what version do you recommend for continuing phaser testing? https://github.com/m-labs/artiq/issues/770#issuecomment-312447608

18:19 <GitHub66> [artiq] jbqubit commented on issue #769: I've flashed that version three times and saw erratic LED blinking each time. That's why I reverted to g07f5e991. What additional information would be helpful? https://github.com/m-labs/artiq/issues/769#issuecomment-312447785

18:59 <GitHub83> [artiq] whitequark closed issue #768: inappropriate error message when using integer constant as boolean https://github.com/m-labs/artiq/issues/768

18:59 <GitHub171> [artiq] whitequark pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/ea7549cfa4efd585a9d115aebb527f4ba097e095

18:59 <GitHub171> artiq/master ea7549c whitequark: compiler: coerce `while` condition to bool....

19:02 <GitHub126> [artiq] jordens commented on issue #769: Does this happen with current master? Does it happen every time? https://github.com/m-labs/artiq/issues/769#issuecomment-312449893

19:08 <jbqubit> rjo: the latest conda build of artiq-kc705-phaser is f4624e08

19:10 <jbqubit> bb-m-labs: force build --props=package=artiq-kc705-phaser artiq-board

19:10 <bb-m-labs> The build has been queued, I'll give a shout when it starts

19:27 <bb-m-labs> build #687 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/687

19:27 <bb-m-labs> build forced [ETA 16m37s]

19:27 <bb-m-labs> I'll give a shout when the build finishes

20:13 <bb-m-labs> build #688 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/688

20:17 <rjo> sb0: could you have a look at defusing that DMA logic path?

20:22 <GitHub47> [artiq] jbqubit commented on issue #769: bb reports timing failed for build of artiq-kc705-phaser for current master. Please let me know when there's a binary available and I'll test again. ... https://github.com/m-labs/artiq/issues/769#issuecomment-312453718

20:24 <bb-m-labs> build #507 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/507

20:24 <bb-m-labs> build #1595 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1595