sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<whitequark> sb0: to finish aqctl_corelog, I need to somehow make CommMgmt usable with asyncio...
<whitequark> irritatingly it looks like run_in_executor doens't let me cancel threads
<sb0> whitequark, can't you just reimplement part of it with asyncio?
<sb0> whitequark, I had proposed a separate socket ...
<sb0> also, threads in python suck, and i'd rather not use them
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<whitequark> sb0: ok, that makes sense
<GitHub185> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/a201a9abd944d08e49f98f382959457cc33763a8
<GitHub185> artiq/master a201a9a Sebastien Bourdeauducq: drtio: multilink transceiver interface
<sb0> _florent_, ^ here is the interface I propose for the synchronized multiple transceiver channels
<GitHub141> [artiq] whitequark pushed 3 new commits to master: https://github.com/m-labs/artiq/compare/a201a9abd944...dd87508a7fc8
<GitHub43> [artiq] whitequark closed issue #691: stream core device log messages to master https://github.com/m-labs/artiq/issues/691
<GitHub141> artiq/master dd87508 whitequark: Implement forwarding of logs from core device to master....
<GitHub141> artiq/master 819440f whitequark: runtime: split log timestamp into secs.micros.
<GitHub141> artiq/master 9e38132 whitequark: artiq_devtool: don't drop data in unpredictable ways (sigh).
<whitequark> \o/
<whitequark> now just the TCP errors
<sb0> mntng, how is the SD card code coming along?
<mntng> got a rtio underflow exception
<sb0> mntng, where?
<bb-m-labs> build #725 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/725
<mntng> have tried putting a delay() before the line where it throws the exception , then the exception happens at other line
<sb0> rjo, I suppose artiq/examples/master/repository/coredevice_examples/pdq2_simple.py needs updating or deleting
<sb0> mntng, okay. can you put your code on https://hastebin.com/ and tell me where the exceptions happens?
<GitHub109> [artiq] sbourdeauducq pushed 2 new commits to master: https://github.com/m-labs/artiq/compare/dd87508a7fc8...377c776ec801
<GitHub109> artiq/master 377c776 Sebastien Bourdeauducq: examples/dma_blink: replay → playback
<GitHub109> artiq/master 9898681 Sebastien Bourdeauducq: aqctl_corelog: only set logging.DEBUG after the server is set up...
<mntng> https://hastebin.com/ijoyuriraq.py , the exception now happens at line 65
<bb-m-labs> build #529 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/529
<bb-m-labs> build #1626 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1626
<sb0> mntng, unrelated but _AD5360_SPI_CONFIG should be renamed. AD5360 is a DAC chip which has nothing to do with a SD card
<sb0> mntng, the set_config_mu() should be removed. it undoes what set_config() does and sets incorrect clock parameters.
<sb0> mntng, response is not 0x01 => response != 0x01
<sb0> mntng, I think the SD card needs CS to be asserted all the time for all the bytes in the command (0x40 0x00 ... 0x95 0xff), is that correct?
<sb0> the SPI core would only assert CS for the duration defined in set_xfer(), i.e. 8 cycles. if you want a continuous CS assertion you need to set the delay() so that the end of the previous write() coicindes exactly with the start of the next write()
<sb0> mntng, are you familiar with using an oscilloscope? it might come handy with debugging this code.
<mntng> i can try to use it.
<bb-m-labs> build #726 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/726
<bb-m-labs> build #530 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/530
<bb-m-labs> build #1627 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1627
<rjo> sb0: yes.
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<rjo> sb0: i am considering moving all of the pdq stuff out of artiq into pdq. what do you think?
<rjo> sb0: mediator, controller, spi driver. the wavesynth stuff can stay.
<sb0> rjo, so pdq would depend on artiq?
<sb0> sounds fine
<sb0> _florent_, did you get the RTM board?
<sb0> chinese 1u enclosures aren't not only better designed than hammond ones, with a lot of machining they also cost barely more than half the price of the uncustomized hammond one, all in single quantities. ridiculous...
<rjo> sb0: some (the artiq) stuff in pdq would depend on artiq.
<sb0> ok
<GitHub21> [artiq] jordens pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/5c66b6376841920032451c593c1f8b8c39e9fcba
<GitHub21> artiq/master 5c66b63 Robert Jordens: setup.py etc: update license
<GitHub177> [pdq] jordens pushed 1 new commit to master: https://github.com/m-labs/pdq/commit/c6d566d364219d9c62d052604a4657d2527f2aae
<GitHub177> pdq/master c6d566d Robert Jordens: make pdq a package
<GitHub125> [pdq] jordens pushed 2 new commits to master: https://github.com/m-labs/pdq/compare/c6d566d36421...e949d0cdd528
<GitHub125> pdq/master e949d0c Robert Jordens: travis: install pdq
<GitHub125> pdq/master 8834e2a Robert Jordens: README: update
<GitHub34> [pdq] jordens pushed 1 new commit to master: https://github.com/m-labs/pdq/commit/78825757f0abc2a3972c1ae86895c24f5fb2e919
<GitHub34> pdq/master 7882575 Robert Jordens: setup.py: no versioneer
<bb-m-labs> build #727 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/727
<GitHub31> [pdq] jordens pushed 1 new commit to master: https://github.com/m-labs/pdq/commit/8551f1c04cd2443f47218c45ab080faa1c72c46a
<GitHub31> pdq/master 8551f1c Robert Jordens: setup.py: install migen/misoc explicitly
<bb-m-labs> build #531 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/531
<bb-m-labs> build #1628 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1628
<GitHub143> [pdq] jordens pushed 1 new commit to master: https://github.com/m-labs/pdq/commit/c45a02f49af6447a89e0f4c193368761ce5a3e52
<GitHub143> pdq/master c45a02f Robert Jordens: setup: move artiq to extras
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<GitHub108> [artiq] jbqubit commented on issue #780: @sbourdeauducq Please comment on the fork. I'd like to get this working in the lab. https://github.com/m-labs/artiq/issues/780#issuecomment-316064793
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<GitHub199> [artiq] sbourdeauducq commented on issue #780: Do the usual debugging. Check your cables and measure the signals at different points. Connect something else than that RTIO PHY (e.g. the MSB of a counter that increments at every cycle, plus OBUFDS) to check that the FPGA itself can toggle logic levels where you want. Double-check RTIO channel numbers. https://github.com/m-labs/artiq/issues/780#issuecomment-316072519
<GitHub127> [artiq] jbqubit commented on issue #691: @whitequark Nice. This works great with Log in ARTIQ Dashboard. :+1: https://github.com/m-labs/artiq/issues/691#issuecomment-316089794
<GitHub66> [artiq] whitequark commented on issue #691: @jbqubit Yes, I specifically made sure that it integrates well with the dashboard. https://github.com/m-labs/artiq/issues/691#issuecomment-316092449
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