<Ishan_Bansal>
Is their any way to write For loop within self.sync block in migen ?
<Ishan_Bansal>
I am getting an error of invalid syntax.
<Ishan_Bansal>
Any documentation regarding this ?
<Ishan_Bansal>
Also how can I write "for" loop within within "If" statement.
<Ishan_Bansal>
sb0 : ping
<attie>
Ishan_Bansal: use list comprehensions. e.g. self.sync += [a[i].eq(b) for i in range(5)]
<attie>
alternatively, you can also have a for loop outside the sync
<attie>
for i in range(5):
<attie>
self.sync += a[i].eq(b)
<attie>
self.sync is just a generic collection of statements with an append operation that accepts both a single statement or an iterable of statements
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<attie>
so the same python syntax rules apply to self.sync += as apply to list.append()/list.extend()
<attie>
i.e. inside an If, only list comprehensions will work: self.sync += If(x==3, [a[i].eq(b) for i in range(5)])
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<GitHub49>
[misoc] enjoy-digital pushed 1 new commit to master: https://git.io/vQDhA
<GitHub49>
misoc/master a3fa71a Florent Kermarrec: cores/sdram_phy/kusddrphy: fix typo on oserdese3/odatain (no functional impact)
<Ishan_Bansal>
attie: If i want to write two statements in the for loop inside the If statement what should I do ?
<Ishan_Bansal>
I mean related to the syntax.
<Ishan_Bansal>
Also is their anyway to write break inside the self.sync block ?
<attie>
the second half of the If statement can contain any number of statements, just separate them by comma: self.sync += If(x, a.eq(b), c.eq(d))
<attie>
there's no break. what hardware is that supposed to make?
<Ishan_Bansal>
attie: but I want both the statement inside the if statement ot beinside the for loop
<attie>
If(x, [a.eq(b) for i in range(5)], [c.eq(d) for i in range(5)])?
<attie>
not sure if it can deal with a list of tuples, you could try if the following works: If(x, [(a.eq(b), c.eq(d)) for i in range(5)])
<attie>
but probably it won't
<Ishan_Bansal>
attie : I want something like If(x, [(a.eq(b), c.eq(d)) for i in range(5)]) but this is not working what can I do in this case ? any suggestions.
<attie>
what's the problem with If(x, [a.eq(b) for i in range(5)], [c.eq(d) for i in range(5)]) ?
<attie>
another option would be to put the for outside the If
<attie>
for i in range(5):
<attie>
If(x, a[i].eq(b), c[i].eq(d))
<attie>
and with the self.sync in there as well of course
<Ishan_Bansal>
sb0 : should I make this function to return some value ?
<attie>
if you want to put it in an If, it needs to return statements.
<attie>
try adding a line "return hello.eq(5)"?
<attie>
I'm also unsure where you are going with this
<attie>
are you sure you don't want to make a submodule?
<Ishan_Bansal>
attie : I am currently working over the RLE module in migen language.
<Ishan_Bansal>
By this I want to calculate the number of bits required for the accumulator_temp, so I want to create a function named entrophycoder.
<Ishan_Bansal>
Within the entrophycoder I want to generate a for loop that keeps on interating each time over the accumulator_temp until it is zero and in the meanwhile divide it by 2 and increase the size by 1.
<attie>
but accumulator_temp is a signal?
<Ishan_Bansal>
the function below is just for the testing purpose over how can I write for or If inside sync.
<attie>
do you want the hardware to do this operation or do you want it to be done before the synthesis?
<Ishan_Bansal>
accumulator temp is a signal.
<Ishan_Bansal>
attie : I want hardware to perform this.
<attie>
then you cannot do it in a function.
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<attie>
you need to write a submodule
<attie>
and if you want to iterate, you need a state machine
<attie>
and a multi-cycle implementation
<Ishan_Bansal>
attie : What is the difference between a submodule and a function ?
<attie>
a function is a way to wrap multiple lines of python.
<attie>
a submodule is a way to wrap migen statements.
<attie>
if you call a function, it will be evaluated at the moment when you generate the verilog
<attie>
so it makes no sense to e.g. divide a signal by 2 in a function, because the signal does not have a value.
<attie>
it represents a wire/reg in the design.
<Ishan_Bansal>
attie: But once written in a function shouldn't it wait for the values to come in the signal ?
<attie>
no
<attie>
that makes no sense whatsoever
<attie>
you have to be clear in your mind about the distinction between the Objects that represent hardware structures (signals and operations) and the python that only manipulates how you stick these objects together
<attie>
if you say Signal(), you create a wire that will end up being placed somewhere in the FPGA as a physical wire
<attie>
this wire will carry different values every cycle
<attie>
but you are only manipulating the connections
<attie>
if you say a.eq(b+c) you are creating a python object of class Op()
<attie>
and another of class Assign()
<attie>
cumulatively, they will end up generating the verilog code to generate the hardware for an adder, and connect the wires represented by the signals b and c to the inputs, and connect the output to the wire represented by the signal a
<attie>
these connections are static
<attie>
but the values they carry will change each cycle
<Ishan_Bansal>
attie : what if I have three signals : a,b,c and I make a function add() as : c.eq(a+b) . Should this work or not ?
<attie>
work in what context?
<attie>
c.eq(a+b) does nothing unless it is added to some module's comb or sync
<Ishan_Bansal>
I am calling this function inside a sync module .
<attie>
that does not mean anything.
<attie>
sync is a list.
<attie>
this list is an attribute of an object of class Module.
<attie>
when you say m=Module(), verilog.export(m)
<attie>
then migen will iterate over the comb and sync lists in m
<Ishan_Bansal>
Is it create a difference if I write the statement c.eq(a+b) or I will call the function add(a,b,c) in general.
<attie>
and generate an equivalent line of verilog in the output.
<attie>
yes.
<attie>
the function add as described has no effect.
<attie>
because a function is not a module, has no attribute comb or sync, and the statement is "forgotten" and migen will never see it.
<Ishan_Bansal>
what if I do self.sync += add(a,b,c) ? does that wok.
<attie>
if you do not explicitly say "module.sync += c.eq(a+b)" and then later export this module (directly or as submodule of your toplevel), migen will never be called on it
<attie>
no, because you did not tell your function to return the statement.
<attie>
if you say add(a, b, c): return c.eq(a+b) that will work
<attie>
but you can only return one statement or a list of statements.
<attie>
any statement that is not in the returned list will be as if it does not exist.
<Ishan_Bansal>
should I use submodule in the same way as I use function in the entrophy coder as above ?
<attie>
there is rarely any practical use to making a function that returns a statement. you can just write the statement directly in the place you would call the function.
<attie>
not exactly.
<attie>
to create a submodule, you make a new class that derives from Module and you add an instance to self.submodules of the module you want to use it in.
<attie>
so e.g. if you want a submodule entropycoder: class EntropyCoder(Module): def __init__(self): ...
<attie>
let's say this module has two input signals a and b: self.a = Signal(), self.b = Signal() and an output signal c: self.c = Signal()
<attie>
there are two ways to add a submodule to a module: by giving it a name as I did above, self.submodule.name = InstanceOfModule
<attie>
then you can access this module under the name self.name
<attie>
migen will turn named submodules into attributes
<attie>
the other way is to say self.submodule += InstanceOfModule
<attie>
then you will no longer have access to the submodule unless you kept some other reference to it
<attie>
e.g. if you say x = InstanceOfModule(), self.submodules += x
<attie>
(sorry note typo I forgot an s above)
<attie>
then you can still access the signals as x.a, x.b, x.c
<attie>
all these Modules, Signals, Statements are just python objects so the regular object oriented programming rules for references etc are in force
<Ishan_Bansal>
ok. that helps, let me try this :)
<GitHub165>
[artiq] sbourdeauducq commented on issue #778: > But it sounds like with SRTIO, I would have to increase all of the FIFO depths to achieve the same effect, which may not be possible given the resource limitations. Would it be possible to relax this restriction?... https://github.com/m-labs/artiq/issues/778#issuecomment-314735070
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<GitHub70>
[artiq] jbqubit commented on issue #780: Here's a stab at this. @sbourdeauducq Please critique the following outline of a commit. @gkasprow Please supply the pin mappings for KC705 LPC. ... https://github.com/m-labs/artiq/issues/780#issuecomment-314922380