sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<GitHub178> [smoltcp] whitequark pushed 2 new commits to master: https://git.io/v7LRf
<GitHub178> smoltcp/master ffe2de7 whitequark: Reorganize EthernetInterface impl. NFC.
<GitHub178> smoltcp/master f31f724 whitequark: Rename RingBuffer::{dequeue_mut→dequeue}, remove RingBuffer::dequeue....
<GitHub32> [smoltcp] whitequark pushed 2 new commits to master: https://git.io/v7LRT
<GitHub32> smoltcp/master c5aa371 whitequark: Fix ICMP error returned by EthernetInterface for unknown IP protocols.
<GitHub32> smoltcp/master c6d4823 whitequark: Clean up socket error handling in EthernetInterface.
<travis-ci> m-labs/smoltcp#155 (master - ffe2de7 : whitequark): The build passed.
<travis-ci> m-labs/smoltcp#156 (master - c5aa371 : whitequark): The build passed.
<travis-ci> batonius/smoltcp#38 (master - c5aa371 : whitequark): The build passed.
<travis-ci> batonius/smoltcp#39 (packet_dispatch - 0b46217 : Egor Karavaev): The build passed.
<GitHub87> [smoltcp] batonius commented on issue #19: Any progress on reviewing this? I keep rebasing the branch just in case. https://git.io/v7L01
<GitHub113> [ionpak] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/ionpak/commit/96489e2b923feeef098c3bc33218b675af2df60a
<GitHub113> ionpak/master 96489e2 Sebastien Bourdeauducq: add missing dimension on enclosure drawing
<GitHub46> [ionpak] sbourdeauducq pushed 2 new commits to master: https://github.com/m-labs/ionpak/compare/96489e2b923f...b3fd5568e5bf
<GitHub46> ionpak/master b3fd556 Sebastien Bourdeauducq: add BoM
<GitHub46> ionpak/master 25f62e3 Sebastien Bourdeauducq: add Kicad design files
<Ishan_Bansal> sb0 : Can we write the index of the signal as another signal ?
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<sb0> Ishan_Bansal, no. create an array of bits of the signal you want to index
<Ishan_Bansal> sb0 : should I create a signal corresponding to every bit of the signal which I want to index ?
<Ishan_Bansal> Also in the below line I am getting a " TypeError: Attempted to convert Migen value to boolean " .
<Ishan_Bansal> What is the best way to write this statement in the correct migen syntax ?
<attie> Ishan_Bansal: you want the binary operators on migen signals, & and | (note that they are bitwise, so only equivalent to the logical "and" and "or" for 1-bit signals).
<Ishan_Bansal> attie : Is their any other way to write the same statement in migen ?
<attie> well, If(hfw_running & ((num_fifo_wrs==0) | (fifo_wrt_cnt+1==num_fifo_wrs), ...) seems the best option to me
<attie> not sure why you would want another
<attie> but you could have multiple If within each other I guess?
<Ishan_Bansal> attie : Also can you help me out in the following error :
<attie> vlc_size_d is a Signal?
<Ishan_Bansal> yes
<attie> then you need to declare vlc_d as Array(Signal(...))
<attie> what is your current declaration of vlc_d?
<mntng> sb0: I'm wondering if this is a normal signal(blue) from miso line after pulling it up, https://pasteboard.co/GCpjwCE.jpg
<Ishan_Bansal> It is a signal at present.
<attie> ok so then change vld_d from Signal(n) to Array(Signal() for _ in range(n))
<sb0> mntng, no, it doesn't look normal
<sb0> mntng, how did you pull it up?
<sb0> mntng, and how is your command sequence like now? can you put the code somewhere?
<attie> but if you use the complete signal elsewhere you need to assign all the bits individually too
<Ishan_Bansal> attie : hm, I think that works.
<attie> the difference is that if you index with a constant it's just selecting an individual wire from the collection of wires that makes up the signal in hardware
<attie> but if you index with a signal you need to create a hardware component to do it (mux)
<attie> so to index with a signal you need a special migen object
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<attie> (the Array)
<GitHub4> [artiq] hartytp commented on issue #778: ... https://github.com/m-labs/artiq/issues/778#issuecomment-317395662
<GitHub3> [artiq] hartytp commented on issue #778: For SRTIO: let's assume we go for 16 FIFOs, each with a depth of ~1e4 events or more.... https://github.com/m-labs/artiq/issues/778#issuecomment-317396344
<GitHub110> [artiq] sbourdeauducq commented on issue #778: > if we can make all of the SRTIO FIFOs something like 1e4 events deep... https://github.com/m-labs/artiq/issues/778#issuecomment-317396680
<GitHub10> [artiq] sbourdeauducq commented on issue #778: > if we can make all of the SRTIO FIFOs something like 1e4 events deep... https://github.com/m-labs/artiq/issues/778#issuecomment-317396680
<GitHub39> [artiq] sbourdeauducq commented on issue #778: > if we can make all of the SRTIO FIFOs something like 1e4 events deep... https://github.com/m-labs/artiq/issues/778#issuecomment-317396680
<GitHub190> [artiq] sbourdeauducq commented on issue #778: To get an idea of what amount of BRAM is reasonable: the FPGA that will support the SAWG is a KU040, with 21.1 mega**bits** of BRAM in total. https://github.com/m-labs/artiq/issues/778#issuecomment-317397938
<GitHub73> [artiq] hartytp commented on issue #778: True, 1e3 events per FIFO is probably more realistic. @dleibrandt @cjbe Would that be enough for you?... https://github.com/m-labs/artiq/issues/778#issuecomment-317398682
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<GitHub46> [artiq] jordens commented on issue #778: **RTIO data width**: This is not all that relevant to SAWG. There it's probably fine to (and that is what splitting a wide event over multiple smaller ones does effectively) increase the minimum time between two events on a channel by a factor of four or so. The event width is most relevant to raw DACs/ADCs that need ~2048 bit per event (at 125 MHz RTIO coarse, 16 GS/s, 16 bit). They would want to be fed bur
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<GitHub74> [artiq] cjbe opened issue #803: "Unknown RPC value tag" error during RPC https://github.com/m-labs/artiq/issues/803
<GitHub17> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/df4f38a1e4d6eeee04c81a60e8b37f2982417ec6
<GitHub17> artiq/master df4f38a Sebastien Bourdeauducq: kc705: add pullup on SD card MISO
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<key2> sb0: doing a sdcard core: https://github.com/lambdaconcept/litesdcard
<key2> sb0: planning to deal with sdr104 (208mhz), have you ever used a sdcard phy for that ?
<sb0> key2, the purpose of the SD card code is to unittest the ARTIQ SPI.
<sb0> not at that speed but milkymist contains code for another native (non-SPI) mode
<sb0> those SD cards are another example of overengineering...
<key2> sb0: how fast ?
<key2> sb0: in what sense ? the voltage switching ?
<key2> or the very complex command system ? ;)
<sb0> I don't remember
<sb0> the command system and the various modes
<bb-m-labs> build #733 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/733
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<bb-m-labs> build #537 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/537
<bb-m-labs> build #1634 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1634
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<GitHub152> [smoltcp] whitequark commented on issue #19: Still working on that refactoring. https://git.io/v7tiB
<GitHub160> [artiq] jbqubit commented on commit 61b0ad1: That NIST is solely mentioned here was once true but is now anachronistic. It is developed by M-Labs for and in partnership with the Ion Storage Group at NIST, Army Research Lab, University of Maryland and Oxford. https://github.com/m-labs/artiq/commit/61b0ad1982f3d292e75cce714516e1559f02709d#commitcomment-23274882
<GitHub119> [artiq] jbqubit commented on issue #779: @sbourdeauducq It there a commit that illustrates the approach you have in mind for this? https://github.com/m-labs/artiq/issues/779#issuecomment-317565305
<GitHub48> [artiq] jbqubit commented on issue #785: Alternately, consider updating installing.rst to include the following. ... https://github.com/m-labs/artiq/issues/785#issuecomment-317568728
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