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<sb0>
rjo, can I kill your flterm?
<rjo>
sb0: yes.
<rjo>
sb0: generally fine most of the time.
<rjo>
sb0: should bits_for(0) really be 1 (and not 0)?
<rjo>
sb0: take the case where i want to determine how many (additional) bits an addition will need. i can use log2_int(len(inputs), need_pow2=False) but bits_for(len(inputs) - 1) seems more idiomatic to me. it's wrong for len(inputs) == 1 however.
<rjo>
because (not 0 > 0) and it takes the path for negative numbers...
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<rjo>
sb0: afaict the most problematic area w.r.t. timing is DMA. in the cases where it fails there are 12 LUTs from the RTIO fifo writable logic into the DMA.
<GitHub166>
[artiq] cjbe opened pull request #759: protocols: increase another asyncio line limit (#671) (master...asyncio_line_limit) https://github.com/m-labs/artiq/pull/759
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<Ishan_Bansal>
Is their any way to provide delay in migen language. As I am writing a test Bench for a program and I am sending some data and than recieving some output, what I want is that the recieve start recieving the data after a certain number of clock cycles.
<Ishan_Bansal>
I tried with the yield but it doesn't seem to work any suggestions
<rjo>
for i in range(delay): yield; and then for d in data: yield recv.eq(data); yield
<rjo>
i assume you are talking about simulation (you give little context)
<Ishan_Bansal>
rjo: I am printing the output but ya its preety much the same thing
<Ishan_Bansal>
rjo: So what is the need of the yield at the last
<rjo>
Ishan_Bansal: next clock cycle. but that's all explained in the documentation.
<travis-ci>
batonius/smoltcp#2 (master - 818fa7d : whitequark): The build passed.
<rjo>
Ishan_Bansal: given that little information one can only speculate.
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<Ishan_Bansal>
The actual and expected output are shown here : https://pastebin.com/BwgMSfFF . The first four values in the Actual output are the garbage values and I want to remove these.
<Ishan_Bansal>
rjo : The above are the printing statements of raw_image.y
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