sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<GitHub49> [artiq] jordens commented on issue #741: We could also just overload repr. https://github.com/m-labs/artiq/issues/741#issuecomment-307013910
<GitHub106> [artiq] sbourdeauducq commented on issue #741: ARTIQ does the right thing in returning an ``eval()``-parseable string in ``repr()``. https://github.com/m-labs/artiq/issues/741#issuecomment-307014103
<GitHub42> [artiq] jordens commented on issue #672: ... https://github.com/m-labs/artiq/issues/672#issuecomment-306911702
<GitHub19> [artiq] jordens commented on issue #741: I don't see this being used or strictly required anywhere. https://github.com/m-labs/artiq/issues/741#issuecomment-307022205
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<Ishan_Bansal> hello everyone , I am writing my code in migen for the dct module and on running simulation It seems that the simulator is going in an infinite loop and when I interrupt it, this shows something like:'https://www.irccloud.com/pastebin/FKzmpohi/' my test module is new_dct_tb.py as follows :'https://github.com/ishan98/litejpeg/blob/master/litejpeg/litejpeg/test/new_dct_tb.py'. Can someone please help me out in this ?
<Ishan_Bansal> Also if you see the dct.vcd formed, it seems that everything goes fine, even the outputs have figure out their valuennings correctly but the only thing is the stimulator is not stop ru
<Ishan_Bansal> *running
<sb0> isn't it just dut.logger.receive() looping?
<sb0> the traceback looks normal
<mithro> sb0: https://github.com/ishan98/litejpeg/blob/master/litejpeg/litejpeg/test/zigzag_tb.py Is pretty similar and seems to terminate fine...
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<rjo> Ishan_Bansal: combinatorial loop? does it always hang in the same cycle?
<GitHub170> [artiq] jordens commented on issue #741: I don't see this being used or strictly required anywhere. https://github.com/m-labs/artiq/issues/741#issuecomment-307022205
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<GitHub157> [artiq] jordens commented on issue #672: With current master, I ran a couple million of these 16 MHz reads and they all passed fine.... https://github.com/m-labs/artiq/issues/672#issuecomment-306911702
<GitHub52> [artiq] jordens commented on issue #672: With current master, I ran a couple million of these 16 MHz reads and they all passed fine.... https://github.com/m-labs/artiq/issues/672#issuecomment-306911702
<GitHub193> [artiq] jordens commented on issue #672: With current master, I ran a couple million of these 16 MHz reads and they all passed fine.... https://github.com/m-labs/artiq/issues/672#issuecomment-306911702
<GitHub194> [artiq] jordens commented on issue #672: With current master, I ran a couple million of these 16 MHz reads and they all passed fine.... https://github.com/m-labs/artiq/issues/672#issuecomment-306911702
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<Ishan_Bansal> rjo : Yes , It is being stuck in only a single loop.
<Ishan_Bansal> rjo : For verification I put a print statement in execute function and as a result it keeps on printing the same text infinite times, indicating that the same loop is being repeated
<rjo> Ishan_Bansal: same **clock cycle**?
<Ishan_Bansal> rjo: How can I found that
<rjo> Ishan_Bansal: just print the clock cycle in your generator.
<rjo> Ishan_Bansal: and obviously make sure you don't have a combinatorial loop in your code.
<Ishan_Bansal> I think the clock cycle is not same for every case, as because when I increase the time of running the code before interrupt and open the .vcd the time shown by the gtkwave software increases indicating increase in the number of clock cycles.
<Ishan_Bansal> rjo : Also I checked my code again and it seems that their is no such loop of combinational logic
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<GitHub64> [artiq] jbqubit commented on issue #40: DRTIO enables increased flexibility with an incremental increase in complexity in the form of implementation-dependent latency compensation. As @jordens pointed out the ARTIQ plan is for an elegant mechanism handle this issue. ... https://github.com/m-labs/artiq/issues/40#issuecomment-307226562
<GitHub23> [artiq] whitequark commented on issue #741: @jordens It's used when debugging, because the user-readable representation can hide some details that may make inference fail. Of course that is not visible from source code. https://github.com/m-labs/artiq/issues/741#issuecomment-307234187
<GitHub126> [artiq] jbqubit commented on issue #563: Please also include JESD204B Subclass 1 in the list. https://github.com/m-labs/artiq/issues/563#issuecomment-307237803
<GitHub95> [artiq] jbqubit opened issue #742: sawg: shot-to-shot variation https://github.com/m-labs/artiq/issues/742
<GitHub5> [artiq] jbqubit opened issue #743: sawg: oscillation when shifting phase https://github.com/m-labs/artiq/issues/743
<GitHub84> [artiq] jordens commented on issue #742: Let's exclude a couple of things (cheap, hacked scope, interactions of cables with scope, missing termination, balun, DAC output stage) on your end first:... https://github.com/m-labs/artiq/issues/742#issuecomment-307248498
<GitHub104> [artiq] jordens commented on issue #743: Most likely a balun/cable/termination/filter/scope effect. Try smaller amplitude https://github.com/m-labs/artiq/issues/743#issuecomment-307248869
<GitHub29> [artiq] jordens commented on issue #743: Most likely a balun/cable/termination/filter/scope effect. Try smaller amplitude https://github.com/m-labs/artiq/issues/743#issuecomment-307248869
<GitHub58> [artiq] jordens commented on issue #743: Most likely a balun/cable/termination/filter/scope effect. Try smaller amplitude, longer/shorter cable, termination at scope, probe actual DAC output etc. https://github.com/m-labs/artiq/issues/743#issuecomment-307248869
<GitHub169> [artiq] jbqubit commented on issue #742: It was a triggering problem with the Rigol scope. Using similar bandwidth Tek scope the shot-to-shot variation goes away. Closing. https://github.com/m-labs/artiq/issues/742#issuecomment-307251799
<GitHub25> [artiq] jbqubit closed issue #742: sawg: shot-to-shot variation https://github.com/m-labs/artiq/issues/742