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<embed-3d>
Hey I'm currently working on a driver for an SGX544 (provided in a31/s & a83t). I'm currently working on getting the gpu clocks properly running. When I deassert the reset in my driver I'm not able to access the registers of the gpu anymore. devmem2 stops and I need to reboot the board. Any idea what the issue might be?
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<KotCzarny>
i think the issuse is it being powervr
<KotCzarny>
*issue
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<embed-3d>
Hmm, I'm using the sunxi reference implementation (kernel 3.x...) and removed the fex stuff and replaced it with devm_get stuff and a probper devicetree binding. So I'm doning nothing really different...
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<KotCzarny>
imagine pvr as a machine inside a machine
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<KotCzarny>
now imagine it crashing or expecting complicated input/initialization
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<wens>
are the clocks enabled?
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<embed-3d>
@wens I'm enabeling them after I deassert the reset, but I tried also to deassert after the clock enable without success
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<embed-3d>
should the clocks be enabled first?
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<wens>
is power enabled? both from the pmic and the prcm?
<wens>
AFAIK you don't need to touch the prcm
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<embed-3d>
On the A83T I'm setting the GPU_PWROFF_GATING_REG to 0 in the R_PRCM and the regulator is enabled
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<embed-3d>
And the bus gating in the ccu is enabled
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<embed-3d>
I just had a look in the datasheet and saw, that there are also in the SMC a register, that mentions the gpu (SMC Master Enable Register). Could this be the rootcase of the issue?
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<wens>
never used it before
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<plaes>
btw.. can someone with A20 to see whether ethernet (gmac) works when it's disable in u-boot?
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<plaes>
and... any idea where to get A80/A31 based devices? :)
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<montjoie>
for A80, only few devices exists like cubie4
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<embed-3d>
wens: I'm doing the following steps maybe that gives an better overview: 1. getting the clocks, the regulator and the reset from dtb 2. set voltage of regulator and enable it 3.set 0 to power off gating 4. deassert reset 5. clk_prepare_enable: bus clk (gating), core clk, mem_clk and hyd clk
<embed-3d>
setting the clock rates is done under point 1
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<megi>
embed-3d: it might be worth checking if something is not also being done on the u-boot side to make GPU access work
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<ndufresne>
paulk-leonov or anyone really, is Hans de Geode around in this channel ?
<ndufresne>
I'm looking forward getting f_uvc (from composite gadget function working), and was wondering if someone had actually tried on sunxi, and knows why it fails
<ndufresne>
meanwhile I'm searching, and learning while at it ;-P
<ndufresne>
(I'm on H5 fwiw
<ndufresne>
and all CDC and serial functions seems to work out of the box)
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<embed-3d>
KotCzarny: you are totaly right. Allwinner is doing some "magic" in their userpace binaries. I'm seeing this behaviour now also with 3.x kernel. Without the userspace stuff is the driver useless.
<embed-3d>
There is a special init, that is located in the blobs...
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<karlp>
we have this "reset64" in sunxi-fel, is there anything that lets us just reset on 32bit stuff too? woudl save me a physical unplug cycle
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<karlp>
I can't find any obvious dangling code in the sunxi-tools repo, aw_rmr_request has a bool for aarch64, but it's always true, and there's no rvbar_reg for h3 et al anyway, even if I hook it up
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