mnemoc changed the topic of #linux-sunxi to: Allwinner/sunxi development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi
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<wens> libv: you mean merge to mainline? ijc and hans
<Turl> libv: haha you'll like this :) http://www.spinics.net/lists/arm-kernel/msg360119.html
<wens> But that spawn the very long thread [0] mentioned
<wens> above and I've zero interest in joining that discussion...
<wens> --
<wens> lol
<Turl> :)
<Turl> good night
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<wens> gn
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<wens> starting to do manual merge of sun6i from u-boot-sunxi to u-boot
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<plaes> wens: good luck
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<libv> hramrach: i was about to send new patches, and a usage mail
<libv> i will also try to send a mail about a31(s)/a23/a33/a80 initial support strategy today
<libv> urgh, our main page looks terrible now
<libv> any thoughts?
<ssvb> libv: do you mean the bold red statements, which are supposed to scare away the users and encourage them to pick some other SoC?
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<libv> it's too bold
<libv> and especially the red one is over the top
<libv> the gpl violations need to be mentioned, but they should not be this bad :)
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<ssvb> the main page nicely represents linux-sunxi as an "advanced" community of blob ridden kernel users
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<philippe_fouquet> hi
<philippe_fouquet> I don't now if is it the good channel?
<philippe_fouquet> I designed a new board from scratch on allwinner A20
<philippe_fouquet> But I can't load on FEL mode
<hramrach> ugh
<philippe_fouquet> wen I run the fel version command I recive all inforation but with the command fel write ... I have a error "libusb usb_bulk_send error -99"
<hramrach> technically, this is the right channel but not many people designing boards
<philippe_fouquet> and the system doesn't respond any more
<hramrach> anyway, FEL is triggered either by all devices being invalid or by changing the leve on some pin of the SoC which is sometimes available as a button on boards
<hramrach> presumably your nand is empty so if it does not work you broke something ;-)
<philippe_fouquet> I uesd the pin UBOOT_SEL (W8) for triged the fel mode
<philippe_fouquet> it sure my nand is empty the board come from the factory
<hramrach> then it should enter fel mode regardless
<libv> hramrach: yes, but that's for a20
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<philippe_fouquet> it enter in fel mode I can get the version with command "fel ver"
<hramrach> you get unusual bulk transfer error
<philippe_fouquet> but that when I used the command "fel write" that I have my error "libusb usb_bulk_send error -99"
<hramrach> yes, that one. does not seem people are seeing this error often
<hramrach> no results from stfw
<philippe_fouquet> and after that if I re used the command "fel ver" i have the errror "libusb usb_bulk_send error -8"
<hramrach> you can try booting from SD if you have a slot
<philippe_fouquet> and I must reset
<hramrach> maybe you have something wired incorrectly in the usb port
<philippe_fouquet> hramrach: you are probably true with some eval board I din't had any problems
<philippe_fouquet> I try to check that
<hramrach> error 99 is "something failed" error
<hramrach> so not much you can learn from that
<philippe_fouquet> often I have "libusb usb_bulk_send error -8" error
<hramrach> if it comes after the 99 error it's already broken
<hramrach> probably
<philippe_fouquet> ok
<hramrach> which would make sense if the previous call failed
<philippe_fouquet> yes it sure
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<philippe_fouquet> I check the usb link
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<philippe_fouquet> when I try to load the u-boot-spl.bin at 0x2000 with command "fel write" where it writed in A20 cache memorie or in DDR3 memorie?
<philippe_fouquet> when I debug the USB command in fel process I could see that the first write (offset sending) it work but it fail when it try to send the data
<mnemoc> you don't have access to the dram at that point
<mnemoc> only sram
<philippe_fouquet> the sram are internal to A20
<mnemoc> yes, inside the SoC
<philippe_fouquet> ok thank
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<mnemoc> u-boot-spl.bin's job is not initialize the dram :p
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<philippe_fouquet> where coudl be my fault the USB link coulbe ok, I can get version, dump, read but i can't right
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<mnemoc> wrong address probably
<philippe_fouquet> write
<philippe_fouquet> i used A20 and i try to write at 0x2000 (like in linux-sunxi.org)
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<arokux> hi guys
<arokux> what is happening in sunxi world in two words? :)
<Montjoie> depends of the size of the word 32 or 64 ?
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<arokux> mm... better 64 :)
<Montjoie> more entropy of choice, but for world conquest I wait for 128, all devs becoming mad (/lib /lib32 /lib64 /lib128)
<arokux> Montjoie: oh, I meant not that detailed info :)
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<wens> ijc: why doesn't u-boot mainline have CONFIG_MACH_TYPE set?
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<ijc> wens: I don't think there's any specific reason, except that mainline kernels don't use it so noone noticed.
<wens> so that's one of the things we need to add back for sunxi 3.4 to work?
<wens> i'm merging sun6i support, so i could just keep that bit in
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<ijc> TBH I don't know what sunxi 3.4 requires, but that sounds very plausible.
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<wens> i don't have any 3.4 setups atm
<ijc> wens: Are you meaning to add upstream, or just add/retain as part of the merge into the github u-boot-sunxi tree? For mach_type I don't mind either way, but I'm not sure what else 3.4 expects of u-boot. FEX support at least I suppose...
<ssvb> wens: there are a few other things needed for sunxi-3.4 - http://irclog.whitequark.org/linux-sunxi/2014-09-07#10113526;
<ssvb> ijc: AFAIK upstream u-boot is actively opposing the addition of mach_type for new boards
<wens> hmm
<wens> that doesn't sound good :(
<ssvb> why?
<wens> ijc: for upstream
<wens> ssvb: if we can't add them to upstream, 3.4 support would be out of the question, wouldn't it?
<ssvb> wens: we are still going to have special sunxi u-boot branches for sunxi-3.4 kernel support, that's not a big deal
<ijc> Well, I'd have to defer on the core maintainers on that question. I don't have a problem with it myself.
<ijc> Although if a fork is needed for other reason I suppose this bit might as well live there too. I'm open to being convinced either way ;-)
<wens> hmm...
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<ssvb> wens: what are you worried about?
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<ssvb> wens: as long as your u-boot patches work fine with the mainline kernel, this should be perfectly fine
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<wens> ssvb: just whether to keep the mach_type define, that's all
<wens> removing it for now
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<dack> I found the absolutely best named AllWinner device... ever.
<dack> "Brand Name: YOUPOO"
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<philippe_fouquet> I come back with my dificulties to communicate in fel mode in A20 cpu
<libv> wens: so you have a columbus board?
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<philippe_fouquet> My USB signal are good (I check it with a scop)
<wens> libv: i have the hummingbird
<wens> for basic bringup purposes, they are the same
<libv> wens: aw, too bad, i wanted to slap someone with ndh again :p
<wens> libv: btw, those patches are for mainline
<libv> yeah, i know
<libv> i just noticed that it included columbus support, so i assumed someone who actually cared about users had a non-ndhed board :)
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<wens> hmm, so the chromebook people are going to add clock-always-on to the DT?
<libv> wens: i haven't followed the discussion, i am pretty tired of that thread.
<philippe_fouquet> I can read the version (fel ver) read ( fel dump or fel read) clear (fel clear) but i can't write (fel write) i have a usb_bulk_send error -99
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<wens> libv: it's the other thread, not the one with 100+ replies
<Turl> philippe_fouquet: where are you trying to write? you can only do so to the sram most likely
<Turl> wens: their problem was with regulators though
<wens> Turl: yeah, but that's because they're using clk_ignore_unused
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<wens> i suppose we could get u-boot to magically add that to the bootargs for simplefb :|
<philippe_fouquet> i try the tuto in linux-sunix.org/FEL/USBBoot ("fel write 0x2000 ./u-boot-spl.bin")
<wens> hmm, maybe you've read it
<philippe_fouquet> my tools work well I test it with a demo board
<libv> if that is what was pasted in this channel yesterday, then i did
<Turl> philippe_fouquet: how big is your ./u-boot-spl.bin?
<philippe_fouquet> Turl: 13 436 B
<Turl> philippe_fouquet: does it work if you write it to 0x4000 ?
<philippe_fouquet> Turl: no same thing ("libusb usb_bulk_send error -99")
<wens> hramrach: could you upload front and back pictures of your q8h board?
<philippe_fouquet> I try to trace in fel and it wrong when it send the data
<Turl> philippe_fouquet: no idea then, maybe a hw bug?
<Turl> do you have a second board to try on?
<Turl> have you tried uboot from a sd card?
<Turl> or livesuit?
<philippe_fouquet> I have 3 board and all have the same probleme for livesuit it the first thing i testing it detect the board and nothing more
<rellla> jemk: i see you're moving forward making big steps :)
<wens> Turl: pll5 on sun6i/sun8i have an extra 'update' bit
<wens> do you thinks it's ok to add support for that to factors clk?
<wens> though set_parent is going to be ugly :(
<libv> feel free to chime in on the naming, i am sure that there will be many opinions on an easy topic like this :)
<rellla> jemk: looking into your deint hack, may i ask why last_id is incremented here? https://github.com/rellla/libvdpau-sunxi/commit/e5ca715dec5a2c5a5a1fc7e162d2c3294d01dc9e#diff-0a0fb553029c4bd5b622ace064642b5aR355
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<Turl> wens: just on pll5?
<Turl> wens: there's not much point in supporting setting pll5 atm, if you do so you're kinda dead :)
<Turl> (dram clk)
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<wens> only usage is mbus :(
<wens> mark brown says: "it seems like we've got to fix simplefb to actually support managing the resources it's using."
<wens> oh, heard today that mediatek is open sourcing all their drivers for mt8127 and mt8135, both tablet socs
<Turl> wens: yeah, but mbus is a child clock, why the :(?
<wens> mbus on a31 is clocked from pll5 by default it seems
<wens> anyway, since we don't do set_rate on it atm, everything is fine
<wens> if we do, parent clock == 0 is going to trigger a div by 0 in the clk driver :p
<wens> (if we add a dummy clock)
<wens> if we don't, i'm not sure what the clk framework would make of a missing parent
<Turl> wens: a dummy for what?
<Turl> why would the parent be zero?
* Turl scratches head
<wens> Turl: dummy for pll5
<wens> placeholder, like we do for pll6 when not implemented
<Turl> wens: you want to implement mbus without implementing pll5?
<wens> Turl: on a23, mbus is clocked from pll6 by default
<Turl> its parent is configurable, you can do so on all the other SoCs as well
<wens> Turl: to implement pll6, i'd like to have mbus (protected)
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<wens> Turl: my goal is to protect mbus, while implementing pll6, and not add pll6 to the protected clock list
<Turl> wens: so you implement pll6 and mbus. you may as well implement pll5 while you're at it, but it's beside the point
<Turl> wens: what's your worry?
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<wens> come to think of it, no worries atm :)
<wens> i'm just overthinking i guess
<Turl> :) ok
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<ssvb> wens: what's going on with pll5 and pll6 in the kernel? are they going to be changing at runtime?
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<wens> ssvb: not yet
<wens> just thinking ahead
<wens> Turl: i vaguely remember reading somewhere that pll6 should always be 600 MHz, but couldn't find it
<ssvb> wens: when configuring mbus clock speed, the dram code for sun5i/sun7i in u-boot may select either of pll5 and pll6
<Turl> wens: it's one of the sata reqs iirc
<ssvb> wens: sunxi-3.4 kernel on sun5i re-configures pll6 to some lower value
<wens> ssvb: if we were to support dvfs for dram, would it be better to select pll6 (relatively fixed clock rate)
<wens> for mbus that is
<ssvb> wens: I don't know, pll6 provides only a limited set of mbus clock speed options
<wens> Turl: there's also 200 MHz (source from PLL6) for cpu mux, but doesn't say how...
<ssvb> wens: both DRAM and MBUS clock speeds affect memory performance - http://linux-sunxi.org/A10_DRAM_Controller_Performance
<ssvb> wens: we don't have enough data yet to decide what would be the best DRAM configuration
<wens> don't quite understand what mbus is... a buffer between the system and dram?
<ssvb> wens: well, nobody knows for sure (we only have scarce comments)
<ssvb> wens: but MBUS is likely the clock speed of the DRAM controller itself, and DRAM is the clock speed of the PHY
<jemk> rellla: good question ;) im not sure how this video ioctls work and if it is correct, but it worked. I think i basically copied it from willswangs libcedarx.
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<ssvb> wens: the DRAM controller is handling requests from 32 host ports, it is able to prioritize and reorder them for better performance, etc.
<ssvb> wens: so yes, it is surely doing some buffering
<rellla> jemk: just wondered about it, because it seems pretty useless for me at that line :p
<jemk> rellla: just to make sure you noticed, its a static variable, it keeps its value
<ssvb> wens: if we want to do dram reclocking, then dram needs to be temporarily put into self-refresh mode
<ssvb> wens: if dram is in the self-refresh mode, then the whole SoC can be even powered down
<ssvb> wens: so basically we are free to re-initialize the dram controller in any way we like, and retain the old data
<ssvb> wens: but of course, we need to clearly know what we are doing and perform all the steps in the correct order (flushing all the queues, etc.)
<ssvb> wens: that's where the actual documentation might be very handy
<ssvb> wens: because the existing code from Allwinner is full of magic constants and is rather scary :-(
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<wens> sounds like a huge task
<rellla> jemk: now i noticed ;)
<ijc> wens: Thanks for that A31 series. Are you intending it to be for v2014.10? If so then it has missed the merge window and we are now post -rc2 (-rc3 must be happening soon) so someone would need to make an (pretty compelling) argument for why it must go in now.
<ijc> Alternatively if you are happy for it to hit v2015.04 we can target that instead.
<ijc> My default position at this stage would be to target v2015.04, but if you want it to land sooner please make a case (on the uboot list please).
<ssvb> wens: it's not huge (we can copy/paste the bits of pm code from the Allwinner kernels), but rather risky
<ssvb> wens: still right now u-boot configures pll6 and pll5 and the dram controller kinda "owns" them
<ssvb> wens: if the kernel tries to manage them too, then everything may get out of control
<ssvb> ijc: sun6i support is clearly too late for v2014.10, nobody is going to bend the rules
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<ijc> ssvb: Agreed, I certainly wasn't going to be making that argument myself.
<Turl> ssvb: right now sata also uses pll6
<Turl> and iirc cedar and mali also feed off of it so it may not be the wisest thing to blindly clock mbus off of
<ssvb> Turl: the current assumption is that pll6 stays at 600MHz, right?
<Turl> I think so
<ssvb> Turl: iirc, cedar and mali use pll4
<Turl> the sata output is 1.2GHz iirc and the other one is 600MHz
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<Turl> hm may be pll4 then
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<ssvb> Turl: MBUS also uses 1.2GHz (that's how we can get 400MHz for MBUS) on sun7i, but is only restricted to 600MHz on sun5i
<Turl> sun5i doesn't have sata though
<ssvb> Turl: yes, and the sunxi-3.4 kernel configures PLL6 to something much lower than 600MHz
<wens> ijc: no 2015.04 is fine
<ssvb> Turl: which may affect dram performance, in the case if the dram controller is clocking mbus from pll6
<ssvb> Turl: do we normally reduce pll clock speeds to optimize power consumption?
<ijc> wens: Ack
<wens> ijc: since no one was working on it, i thought i'd get things started
<Turl> ssvb: checking 3.4 quickly, pll6 is also potentially used for usb and other stuffs
<Turl> ssvb: no, we shut them off :)
<wens> yeah, some part of the docs mentions usb 24M being clocked from pll6
<wens> in the clock diagrams i think
<ssvb> wens: isn't it the other way around?
<wens> ssvb: "USB 24M", not the 24M osc
<Turl> bbl
<ijc> wens: Ack, thanks for doing so!
<wens> can't find it :|
<wens> hmm, a10 manual lists pll6 as "fixed to 1.2 GHz"
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<wens> ssvb: ok, i probably mixed things up
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<ssvb> Turl: the 3.4 kernel has some rather nasty hardcoded divisors, and also some nasty defines like '#define MMC_SRCCLK_PLL6 "sdram_pll_p"'
<ssvb> Turl: so that the PLL6 identifier in the code sometimes actually means PLL5
<ssvb> Turl: a funny grep exercise to find all this junk...
<ssvb> Turl: almost like the classic '#define TRUE FALSE' :)
<wens> hehe, that one screws everyone
<Turl> ssvb: heh
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<ricardocrudo> I'm following the http://linux-sunxi.org/U-Boot guide to build the u-boot for Itead A20 core board. When I try to boot it the u-boot hangs.minicom output: http://pastebin.com/raw.php?i=CaHapu1Q
<ssvb> ricardocrudo: how are you writing this u-boot to the sd card?
<ricardocrudo> ssvb: dd if=u-boot-sunxi-with-spl.bin of=/dev/sdX bs=1024 seek=8
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<ricardocrudo> ssvb: I tried build the u-boot in DEBUG mode to get more verbose outuput but I can't. The build returns .sram overflowed
<ssvb> ricardocrudo: what is your gcc version?
<ssvb> ricardocrudo: or actually https://www.mail-archive.com/linux-sunxi@googlegroups.com/msg05406.html (but unfortunately there was no further feedback)
<ssvb> ricardocrudo: also the "Failed to set core voltage! Can't set CPU frequency" message is rather suspicious
<wens> Turl: a bunch of fixes for 8250 dma: http://git.breakpoint.cc/cgit/bigeasy/linux.git/log/?h=uart_v8
<wens> most of it omap related though
<ricardocrudo> ssvb: arm-none-eabi-gcc --version = 4.8.3, from debian testing repo
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<ssvb> ricardocrudo: it's hard to say what's wrong, supposedly everything should work fine
<ssvb> ricardocrudo: except that Iteaduino_Plus_A20 is not a very popular board around here and I'm not sure if it is really well supported
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<astr> sorry buts whats the git command to download the revision tree (is that what it's called?) of just the latest version of sunxi uboot for olimex lime-a10?
<ricardocrudo> ssvb: I see. And how about "spl: not an uImage at 1600" do you know what this means?
<libv> astr: info git-clone
<libv> astr: look for depth
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<astr> libv, thanks but I think I asked to wrong question. I'm trying to folow these instructions http://olimex.wordpress.com/2013/12/13/building-debian-linux-image-for-a10-olinuxino-lime-with-kernel-3-4-67 but I don't understand
<astr> .....
<astr> git rev-parse --verify HEAD 4e491b03b53bd89af3065fc325a99106d0161998
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<astr> ....I'm at the stage of compling uboot
<astr> they talk of "next branch", whats that?
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<ZetaNeta> Hi
<ZetaNeta> News on A80?
<ZetaNeta> Any devboards on it? (Didnt come here for a while)
<ZetaNeta>
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<oliv3r> lo
<ZetaNeta> ricardocrudo, Yeah, heard about it, but is it being sold anywhere?
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<hramrach> they actually make tablets with an A80, lulz
<ZetaNeta> rafaelMOD: Delivery is more than half of the thing itself.
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<ZetaNeta> Optimus is abit more than a "Quite well packed" CubieTruck (http://onpad.ru/shop/cubie/cubietruck/1379.html)
<ZetaNeta> I wonder, which one should i take
<ZetaNeta> I need one for a "Full, Gentoo-user, desktop", and another for a hardcore wearable project
<ZetaNeta> And cant really choose
<ZetaNeta> I want something powerful for both
<ZetaNeta> And been searching for A80, everytime i remember about it
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<cubear> Are any A80 boards out yet?
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<ZetaNeta> Optimus, and pcduino 8 looks like some
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<astr> to compile a new kernel for the olimex lime do I need to also comple uboot?
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<diego71> astr: which linux? sunxi or mainline?
<astr> diego71, sunxi
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<diego71> astr: no need to change uboot
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<astr> diego71, arr good but then again... theres a bug when I first plug the power cable in the board boots but fails due to bad kernel image checksum, i think(?) then I press the power on button for a few secs the board does a forced powers off then I press the power button again and it boots successfully is this a bug fixed in a newer uboot?
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<diego71> ssvb: mainline u-boot should support changing mbus clock, right? But it looks like not: http://git.denx.de/?p=u-boot.git;a=blob;f=board/sunxi/dram_sun7i_384_1024_iow16.c;h=04e4b1e9b99d5a65ff3009f0b07fe9cb6ff789dd;hb=HEAD
<diego71> astr: it's possible. But I never had this kind of problem
<astr> diego71, ok thanks muchly
<ssvb> diego71: http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/include/asm/arch-sunxi/dram.h;h=1945f75441f4dce6cb0609527edf028e4512cd15;hb=HEAD#l72
<ssvb> diego71: if you don't explicitly initialize some parameter in the 'dram_para' struct, it gets assigned a default 0 value (which is interpreted as 300 for mbus_clock)
<diego71> ssbv: ok, now I understand
<diego71> ssbv: i'm going to do some test also on a a13-olinuxino, using mainline u-boot
<ssvb> diego71: the mainline u-boot is not going to work well out of the box, I'm still preparing the patches for a proper sunxi-3.4 support
<ssvb> diego71: a13-olinuxino? or a13-olinuxino-micro?
<diego71> ssvb: a13-olinuxino
<diego71> ssvb: which kind of problem can I have?
<ssvb> diego71: also the default environment is different in the mainline u-boot
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<ssvb> diego71: how is the emr1 test progressing on a20?
<diego71> ssvb: I tested with 0x44 and I didn't see much difference from 0x4
<diego71> ssvb: now I'm testing 0x40
<ssvb> diego71: ok
<ssvb> diego71: I forgot to mention that you don't need to wait for completion of the additional 'hardening' tests, which try to run 100 rounds of memtester for each config
<ssvb> diego71: this only makes sense for testing the 'final' configuration
<diego71> ssvb: thanks, i've already found out during the previus tests...
<ssvb> diego71: yeah, it's kind of intuitive, but sorry for not explicitly mentioning this earlier
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<ssvb> diego71: can you still upload the emr1=0x44 results?
<diego71> ssvb: of course
<ssvb> diego71: thanks, it's just interesting if it is maybe slightly better or slightly worse
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<diego71> ssvb: done, i pasted also 0x40 case
<diego71> It looks slightly worse
<ssvb> diego71: yes, indeed
<ssvb> diego71: and it looks like 0x40 is also going to be worse than 0x4 when it runs to completion
<diego71> ssvb: and I expect 0x0 to be even worse ...
<diego71> ssvb: I wonder if it's better start to play with zq, leaving emr1=0x4
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<diego71> ssvb: about uboot mainline and A13, it looks like the second commit it's not needed for A13 (sun5i)
<ssvb> diego71: do you have the machine id already defined in your u-boot environment?
<ssvb> diego71: or maybe it does not actually do a strict check for the machine id if u-boot does not define one
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<diego71> ssvb: I don't know
<ssvb> diego71: about emr1=0x4, it looks like Olimex people have selected the 330 ohm resistor for a reason, essentially doing impedance configuration in a hardware way instead of configuring it in software :)
<diego71> I've to look better, but I think that I'm going to sleep now
<ssvb> diego71: but nevertheless, it's good to confirm that emr1=0x4 is already the best value
<ssvb> ok, good night
<diego71> ssvb: it's possible, expecialy if they had changed the impedence
<diego71> thanks
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