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<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/vHIhW
<openfpga-github> openfpga/master a38304c Andrew Zonenberg: Continued work on DAC support. See #32
<openfpga-github> [logtools] azonenberg pushed 1 new commit to master: https://git.io/vHIje
<openfpga-github> logtools/master 1bd2c28 Andrew Zonenberg: Indentation fixes to LogDebugTrace
<openfpga-github> [openfpga] azonenberg pushed 2 new commits to master: https://git.io/vHIjv
<openfpga-github> openfpga/master ab976c9 Andrew Zonenberg: Updated to latest logtools
<openfpga-github> openfpga/master 0c82c38 Andrew Zonenberg: Greenpak4Netlist: Removed "verbose" argument from IndexNets() because we now have LogTrace()
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<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/vHLfV
<openfpga-github> openfpga/master 39f583b Andrew Zonenberg: Finished initial DAC support. Fixes #32. DRC could probably be better?
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<azonenberg> There goes initial DAC support driving them from GP_COUNTx cells
<azonenberg> Working on inference of counters with POUT now
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<openfpga-github> [yosys] azonenberg pushed 1 new commit to master: https://git.io/vHLTK
<openfpga-github> yosys/master 184bd14 Andrew Zonenberg: greenpak4_counters: Added support for parallel output from GP_COUNTx cells
<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/vHLTQ
<openfpga-github> openfpga/master 7899229 Andrew Zonenberg: Various tweaks to Dac test case. Updated documentation to reflect that inference of parallel counter outputs to DACs is now supported
<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/vHLT5
<openfpga-github> openfpga/master 348a2bd Andrew Zonenberg: Dac test: Updated comment in code to reflect actual clock frequency
<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/vHLTF
<openfpga-github> openfpga/master 7c3f981 Andrew Zonenberg: Fixed typo in comment
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<pie_> a bunch of good looking abstracts on this site but of course no aper
<pie_> *papers
<pie_> ok turns out i just cant read and everything is up on super sekrit library
<pie_> ISTFA != ITSFA
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<openfpga-github> [yosys] azonenberg pushed 1 new commit to master: https://git.io/vHtOq
<openfpga-github> yosys/master e0386d0 Clifford Wolf: Merge pull request #346 from azonenberg/master...
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<openfpga-github> [yosys] azonenberg pushed 3 new commits to master: https://git.io/vHtAg
<openfpga-github> yosys/master dca3b3c Clifford Wolf: Add examples/osu035
<openfpga-github> yosys/master 664ba4d Clifford Wolf: Merge branch 'master' of github.com:cliffordwolf/yosys
<openfpga-github> yosys/master 2122ae6 Clifford Wolf: Add workaround for CBMC bug to SimpleC back-end
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