<azonenberg>
And kinda small, 64 Mb (256 Mb / 32 MB total for 4)
<azonenberg>
but i didnt need a ton of capacity for this design
<azonenberg>
Four of them is the equivalent bandwidth of a DDR3 667 x16 chip
<azonenberg>
The final version of this design is going to be four DDR3 x16 (or eight x8, TBD) and four of the samtec headers on the right instead of one
<azonenberg>
then 1g and 10g ethernet
<azonenberg>
This was hand assembled, even the 0201 terminators on the diff pairs
<azonenberg>
and reflowed in my garage toaster oven
<azonenberg>
The full version will also use a (most likely) 676 ball FPGA
<azonenberg>
oh, the other nice thing about hyperram is that it's 1mm pitch instead of 0.8mm
<azonenberg>
So super easy to lay out on a batch fab with large design rules
<davidc___>
azonenberg: homemade linear stage with <0.0001" precision
<azonenberg>
niiice
<azonenberg>
whats the purpose?
<azonenberg>
i assume your talk isnt on stage design
<davidc___>
azonenberg: for my cross-sectioning-pcbs-for-netlist-discovery
<azonenberg>
oooh
<azonenberg>
wait cross sectioning?
<azonenberg>
like full on tomography
<davidc___>
azonenberg: yup
<azonenberg>
and imaging end-on?
<azonenberg>
innnteresting
<davidc___>
azonenberg: yup
<azonenberg>
i want it :p
<azonenberg>
sounds far superior to trying to do a super even planar delayer
<davidc___>
azonenberg: like surface grinding in terms of process, but with 1 less axis of control, and less precision required
<davidc___>
azonenberg: yup
<davidc___>
azonenberg: hence why I'm doin a talk on it
<azonenberg>
yeah you're doing the same volumetric dataset
<azonenberg>
just transposing the matrix
<davidc___>
azonenberg: pretty much
<azonenberg>
you have this working?
<davidc___>
azonenberg: by hand yes, automated, well, thats a race to the talk day :)
<azonenberg>
lol
<azonenberg>
i see
<davidc___>
azonenberg: I was going to pull the talk (in fact, I did try to pull the talk)
<davidc___>
to present when I had the automation working
<davidc___>
but they convinced me to still present
<davidc___>
so eh,
<azonenberg>
Lol
<davidc___>
azonenberg: oh, and all of that was made in my shop on a manual lathe and mill
<azonenberg>
Awesome
<davidc___>
excluding fasteners, and the T5 pulley)
<azonenberg>
in other news, idk if you saw the chatter here earlier
<azonenberg>
i'm getting back into the coolrunner game
<davidc___>
yeah, saw that
<azonenberg>
me and rqou figured out 100% of the 2c32a bitstream at this point (including the stuff i didn't have at my last recon talk) and are working on scaling up to bigger devices
<davidc___>
niiice
<azonenberg>
i'm also going to try to make a unified greenpak/coolrunner bitfile to verilog flow
<davidc___>
pretty soon itll be a full CPLD PAR
<davidc___>
oh, wait, bitfile to verilog
<davidc___>
even cooler
<azonenberg>
So
<azonenberg>
the greenpak tools are already a full cpld par
<azonenberg>
i'm trying to make it a generic par engine
<azonenberg>
with greenpak and coolrunner as back ends
<azonenberg>
but i'm also trying to go the other way
<azonenberg>
a cool PoC would be porting a coolrunner bitfile to a logically equivaletn greenpak design
<azonenberg>
or vice versa
<azonenberg>
Inferring greenpak hard IP along the way
<azonenberg>
i'm going to try and use this as the base of my "hardware IDA" pipe dream
<azonenberg>
at this point i have two fairly distinct (one lut and one pla based) architecture well understood
<azonenberg>
i could do ice40 as well, thats documented but i would have to spend some time learning my way around it
<azonenberg>
So i could have those all supported as input formats
<azonenberg>
davidc___: this is on top of me trying to finish the greenpak compiler
<azonenberg>
i'm almost done with the slg4662x
<azonenberg>
the 46140 is going to need a bit more work but once the 4662x is done it should follow pretty quickly
<azonenberg>
i just havent actually done any work on it at all :p
<azonenberg>
at that point i'd have full gp4 support
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<davidc___>
azonenberg: sweet. I'm gonna have to try all that stuff one of these days
<davidc___>
I've been focusing almost solely on the PCB stuff for the last 6mo, so once thats done, I'll be free to play more with FPGAs
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<alibaba__>
Hi. I wonder if someone knows a way to directly write the config RAM in an Altera MAX II?