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<openfpga-github> [openfpga] azonenberg pushed 3 new commits to master: https://git.io/vH4GW
<openfpga-github> openfpga/master 8eee84a Andrew Zonenberg: Greenpak4Device: Added WriteToBuffer()
<openfpga-github> openfpga/master 3c5e8bc Andrew Zonenberg: doc: Fixed line length issue
<openfpga-github> openfpga/master 59125e2 Andrew Zonenberg: Greenpak4Device: Refactored GenerateBitstream() into separate member fn
<azonenberg> Hmm
<azonenberg> whitequark: Why do we have Greenpak4Device::GREENPAK4_PART and SilegoPart enums both?
<azonenberg> shouldnt they be the same?
<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/vH4ZE
<openfpga-github> openfpga/master 9e24e43 Andrew Zonenberg: More initial work on timing characterization stuff
<whitequark> azonenberg: one of them uses the actual devboard ids as values
<whitequark> and I'm not sure about 45520/45521
<azonenberg> ah yeah ok
<azonenberg> so its die IDs vs SKUs
<azonenberg> Makes sense
<azonenberg> whitequark: also btw i am maybe an hour of work short of having fully scripted (rising edge only, for now) propagation delay measurements for slg46620v elements across the 3.3V +/- 0.15V voltage range
<whitequark> wonderful
<azonenberg> No setup/hold
<azonenberg> no temperature corners
<azonenberg> Process corners require manual die swap obviously
<azonenberg> But this is a start
<azonenberg> i just finished turning my old manual command line driven delay measurement app (running on starshipraider) into a socket server that i can call out to
<azonenberg> and i made some refactoring to libgreenpak4 so that you can export a bitstream directly from a Greenpak4Device to libgpdevboard without going to a file first
<azonenberg> I even made a test bitstream in memory, bypassing the HDL step entirely, that just drives one io pin to a constant
<azonenberg> only missing part is to write the glue to make that app call out to the delay measurement instrument
<azonenberg> then do a loop that goes across the voltage corners (3.3V only until i add level shifters)
<azonenberg> and loops over various design elements
<azonenberg> to measure delays
<azonenberg> also have to add a switchable inverter to my fpga image to do falling edges
<rqou> azonenberg: what happened here? "FB0 pad 5 (row 5, 16, 27, 5)"
<rqou> note the duplicated 5
<azonenberg> huh
<azonenberg> pretty sure thats 35
<rqou> 38/39 are missing
<rqou> so it's probably those
<rqou> fix plz :P
<azonenberg> yeah gimme a sec
<azonenberg> 38 is FB1_6_IBUF which is FB0 pad 5
<azonenberg> 39 is FB1_7_IBUF which is FB0 pad 6
<azonenberg> It was 2am and i was tired :P
<openfpga-github> [openfpga] azonenberg pushed 2 new commits to master: https://git.io/vH4Wm
<openfpga-github> openfpga/master 57abc63 Andrew Zonenberg: Fixed typo in coolrunner docs
<openfpga-github> openfpga/master 1793163 Andrew Zonenberg: Added xptools
<azonenberg> This is going to be quite the chain of toolling
<azonenberg> From gp4tchar (characterization driver)
<azonenberg> i have a USB connection to the greenpak devkit
<azonenberg> then a TCP connection to GreenpakTimingTest
<azonenberg> Which has a TCP connection to nocswitch
<azonenberg> Which has a TCP connection to jtagd
<azonenberg> Which has a JTAG connection to starshipraider
<azonenberg> Which has a LVCMOS33 connection to the greenpak devkit
<azonenberg> This will get a lot simpler once i get a socket server running on starshipraider
<azonenberg> then i can cut all the middlemen
<rqou> azonenberg: there's an error here too:
<rqou> XC2ZIAInput::IBuf{ibuf: 28},
<rqou> er
<rqou> FB1 pad 13 (row 2, 12, 28)
<rqou> FB1 pad 12 (row 10, 16, 31, 12)
<rqou> 12 is there twice
<rqou> probably should be 39?
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<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/vH4yb
<openfpga-github> openfpga/master 47eba72 Andrew Zonenberg: Continued work on GreenPAK timing characterization
<rqou> azonenberg: what happened to this?
<rqou> FB1 pad 13 (row 2, 12, 28)
<rqou> FB1 pad 12 (row 10, 16, 31, 12)
<rqou> 12 is duplicated
<azonenberg> rqou: i have it saved
<azonenberg> just wanted to push the work i did earleir today before bed
<azonenberg> i was out in the woods looking for two missing kids half the night when i could have been coding
<rqou> aah
<azonenberg> i'll get to that in the morning once i'm more awake :p
<rqou> ok
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<rqou> hmm, something strange
<rqou> do unused FFs toggle with GCK0?
<rqou> that seems like it wastes power unnecessarily
<rqou> but i don't see anything that can disable taht
<rqou> wait no they don't toggle obviously
<rqou> but they will read their garbage inputs and forward them to their outputs
<rqou> no wait
<rqou> yeah it seems this does happen
<rqou> hmm
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<rqou> hmm the xilinx .jed parser isn't _completely_ scanf-based
<rqou> it does still have some intelligence
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<rqou> azonenberg: what happens if i try to use a zia row where i haven't enabled anything at all?
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<rqou> azonenberg: hmm xilinx actually does seem to have a real jed parser
<rqou> i think i somehow just messed it up when i was testing before
<rqou> maybe i forgot the * at the end of the line or something
<rqou> yeah i messed it up before
<rqou> except xilinx doesn't support the F field
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<rqou> they output it but can't actually read it
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<azonenberg> rqou: So, there is no "havent enabled anything"
<azonenberg> the all-idle row ties it to a constant value because one of the pass transistors is a pfet instead of a nfet
<azonenberg> You'd need to invert that bit to turn off ALL pass transistors
<rqou> but what if I do write 01111111?
<rqou> what happens?
<azonenberg> It looks like there's a weak keeper/pull circuit to keep it somewhat stable
<azonenberg> sec
<azonenberg> There's weak feedback from the first inverter stage to the input of the row driver
<azonenberg> OGATE keeps the row driver stable until config is finished
<azonenberg> so whatever value that drives, will stay
<azonenberg> also LOLOLOL https://twitter.com/SilegoTech
<azonenberg> the chip vendor is retweeting my characterization on their silicon
<cr1901_modern> They must like you...
<rqou> hmm what's the default state of gck if it's not used?
<azonenberg> cr1901_modern: lol yeah i cannot imagine @XilinxInc etc doing that
<rqou> it matters, because latches :P
<azonenberg> rqou: Good question
<azonenberg> Figure it out :D
<rqou> also, i just realized that we don't know _exactly_ where the global buffers are hooked up to
<rqou> e.g. can i drive a global buffer from an internally-sourced signal?
<rqou> what if the output buffer is disabled?
<rqou> and does clkop work on latches?
<rqou> how do i even write a latch in verilog? :P
<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/vHReU
<openfpga-github> openfpga/master 0cf1ba4 Andrew Zonenberg: Fixed another ZIA matrix typo
<rqou> yeah, it seems we're missing a bit of info on latches :P
<rqou> it's almost like nobody uses those
<azonenberg> I believe the global buffers are sourced directly from the IBUF
<azonenberg> a latch is an always @(*) block that does not always write to a given value
<azonenberg> always @(*) if(le) dout <= din;
<rqou> right, so clkop works on latches
<rqou> i wonder what happens if i set the clkfreq bit on a latch?
<azonenberg> lol
<azonenberg> so clkop inverts latch enable?
<rqou> yeah
<azonenberg> 0 = transparent when high
<rqou> "rising edge" => latch passes through when clock is 1
<azonenberg> ok
<rqou> so yeah, 0 = transparent when high
<rqou> please don't set the ddr bit :P
<rqou> the clock nets seem to behave as 0 if not enabled
<azonenberg> what does the ddr bit do? lol
<rqou> i actually didn't test it
<pie_> dance dance revolution
<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/vHRJ0
<openfpga-github> openfpga/master 3e5a39a Andrew Zonenberg: Added clarification for behavior of FF clock inverter
<azonenberg> pie_: its funny
<rqou> wow, so many weebs here :P
<azonenberg> whenever i see one of those things in an arcade
<azonenberg> i think "double data rate"
<azonenberg> :P
<pie_> ive never played that game actually
<azonenberg> Me neither
<azonenberg> but i've seen it
<rqou> i guess i have the highest weeb level
<rqou> i've actually played it
<rqou> but i'm no good at it
<azonenberg> rqou: but have you played it in a Sailor Moon outfit? :p
<rqou> no
<azonenberg> (weeb level: 9001)
<pie_> hav you imagined playing it in a sailor moon outfit?
<azonenberg> pie_: that was just the first anime character that came to mind
<pie_> i meant rqou
<azonenberg> b/c $WIFE has a bunch of paraphernalia around
<pie_> azonenberg obviously has
<azonenberg> (yes, i married a weeb)
<pie_> because is he hasnt, he has now
<pie_> azonenberg, xD awesome
<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/vHRU7
<openfpga-github> openfpga/master a55ed2c Andrew Zonenberg: Fixed typo
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<rqou> hmm if set and reset are both asserted, who wins?
<azonenberg> rqou: probably oscillates
<azonenberg> either that or bus fight depending on how the ff is built
<cr1901_modern> why would set and reset share the same wire?
<azonenberg> they arent
<azonenberg> but if you drive S and R on the same ff simlutaneously
<azonenberg> who knows how its built
<cr1901_modern> well I don't understand the "bus fight" part
<cr1901_modern> which would be the condition that both S/R are driving the same conductor
<azonenberg> well, if you have the FF built like a sram cell
<azonenberg> where you have an inverter loop then drive a value into it
<azonenberg> simultaneous S and R would basically be a power-to-ground short through the two bitlines
<cr1901_modern> Do you have a schematic?
<azonenberg> no
<azonenberg> i have low reoslution images that dont cover enough of the macrocell to be useful
<azonenberg> Fixing that is on my TODO
<azonenberg> the SEM at work is under maintenance right now and i'm not trained on the polisher
<rqou> poke digshadow to image it again?
<azonenberg> so once thats fixed i'll do it myself
* azonenberg is in the process of working out with the boss arrangements for getting sem/fib time off the clock for a reasonable fee
<azonenberg> cr1901_modern: so thats a 6T cell
<azonenberg> an 8T cell has two bitlines
<azonenberg> and two copies of M5/M6
<cr1901_modern> Ahhh for S/R functionality?
<azonenberg> But if both are active at once you get a bus fight between the bitlines
<azonenberg> I have no idea how this FF is built
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<cr1901_modern> azonenberg: Also, AFAICT in that linked circuit it's asynchronous
<cr1901_modern> which isn't true for flip flops
<azonenberg> Well a latch is async
<azonenberg> a FF can be made from an edge detector and a latch
<cr1901_modern> Oh... TIL. Makes sense, but I never put two and two together :P
<cr1901_modern> I am guessing the two bitlines are required for S/R functionality?
<cr1901_modern> are a requirement*
<azonenberg> for sram, they're differential
<cr1901_modern> NOT x and x?
<azonenberg> yeah
<azonenberg> to read, measure bl1 - bl2 with a diff amplifier
<azonenberg> to write, drive x and !x
<cr1901_modern> So that 6T has two bitlines too
<azonenberg> Yes
<azonenberg> 8T has four bitlines
<azonenberg> two diff pairs
<azonenberg> for dual port memory
<azonenberg> you can do two reads or one write and one read to the same cell
<azonenberg> Two writes are undefined
<cr1901_modern> (5:19:18 PM) azonenberg: an 8T cell has two bitlines <-- :D
<cr1901_modern> In any case, now my confusion is alleviated lol
<azonenberg> i meant, twodiff pairs
<azonenberg> Anyway, it depends on how they built the ff
<azonenberg> there may be a mux or something
* cr1901_modern only comes with a -pedantic switch, sorry
<azonenberg> so simultaneous s+r resolve well defined
<cr1901_modern> Thanks for the help, azonenberg
<cr1901_modern> Remind me to buy you a covfefe if we ever meet
<azonenberg> Lol
<azonenberg> Did you see my tweet? :p
<azonenberg> its an opcode :p
<cr1901_modern> lmfao
* jn__ opens twitter.com/azonenberg
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<jn__> which architecture is that, though? i would have guessed x86(64), but i can't find it in the intel menual
<jn__> -typo
<azonenberg> jn__: fictional
<azonenberg> though i wrote it in the style of the x86 manuals
<jn__> ok, good :)
<cr1901_modern> 256 coverage counters, huh?
<azonenberg> hey if trump ever designed a cpu
<azonenberg> the performance counters would be yuuuge
<jn__> i have instructions, i have the best instructions
<cr1901_modern> The best, most powerful performance counters in the world
<lain> the best performance counters in the history of performance counters, possibly ever
<qu1j0t3> SAD!
<azonenberg> jn__: i actually looked
<azonenberg> to see if any common isa had a "COV" opcode
<azonenberg> none did
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<azonenberg> (would have been even better of the opcode was 0xfefe)
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<rvense> i don't think i've seen the internet so united behind one joke since all your base were belong to us.
<cr1901_modern> I want covfefe to become America's "Ed Balls Day"
<rvense> think i missed that one?
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<cr1901_modern> A British politician called Ed Balls accidentally tweeted his name. Because the word "Balls" is funny, it became a meme and national holiday
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<rvense> harh
<rvense> there was also the time brett easton ellis tweeted "come over, bring coke"
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