<openfpga-github>
[openfpga] azonenberg pushed 3 new commits to master: https://git.io/vH4GW
<openfpga-github>
openfpga/master 8eee84a Andrew Zonenberg: Greenpak4Device: Added WriteToBuffer()
<openfpga-github>
openfpga/master 3c5e8bc Andrew Zonenberg: doc: Fixed line length issue
<openfpga-github>
openfpga/master 59125e2 Andrew Zonenberg: Greenpak4Device: Refactored GenerateBitstream() into separate member fn
<azonenberg>
Hmm
<azonenberg>
whitequark: Why do we have Greenpak4Device::GREENPAK4_PART and SilegoPart enums both?
<azonenberg>
shouldnt they be the same?
<openfpga-github>
[openfpga] azonenberg pushed 1 new commit to master: https://git.io/vH4ZE
<openfpga-github>
openfpga/master 9e24e43 Andrew Zonenberg: More initial work on timing characterization stuff
<whitequark>
azonenberg: one of them uses the actual devboard ids as values
<whitequark>
and I'm not sure about 45520/45521
<azonenberg>
ah yeah ok
<azonenberg>
so its die IDs vs SKUs
<azonenberg>
Makes sense
<azonenberg>
whitequark: also btw i am maybe an hour of work short of having fully scripted (rising edge only, for now) propagation delay measurements for slg46620v elements across the 3.3V +/- 0.15V voltage range
<whitequark>
wonderful
<azonenberg>
No setup/hold
<azonenberg>
no temperature corners
<azonenberg>
Process corners require manual die swap obviously
<azonenberg>
But this is a start
<azonenberg>
i just finished turning my old manual command line driven delay measurement app (running on starshipraider) into a socket server that i can call out to
<azonenberg>
and i made some refactoring to libgreenpak4 so that you can export a bitstream directly from a Greenpak4Device to libgpdevboard without going to a file first
<azonenberg>
I even made a test bitstream in memory, bypassing the HDL step entirely, that just drives one io pin to a constant
<azonenberg>
only missing part is to write the glue to make that app call out to the delay measurement instrument
<azonenberg>
then do a loop that goes across the voltage corners (3.3V only until i add level shifters)
<azonenberg>
and loops over various design elements
<azonenberg>
to measure delays
<azonenberg>
also have to add a switchable inverter to my fpga image to do falling edges
<rqou>
azonenberg: what happened here? "FB0 pad 5 (row 5, 16, 27, 5)"
<rqou>
note the duplicated 5
<azonenberg>
huh
<azonenberg>
pretty sure thats 35
<rqou>
38/39 are missing
<rqou>
so it's probably those
<rqou>
fix plz :P
<azonenberg>
yeah gimme a sec
<azonenberg>
38 is FB1_6_IBUF which is FB0 pad 5
<azonenberg>
39 is FB1_7_IBUF which is FB0 pad 6
<azonenberg>
It was 2am and i was tired :P
<openfpga-github>
[openfpga] azonenberg pushed 2 new commits to master: https://git.io/vH4Wm
<openfpga-github>
openfpga/master 57abc63 Andrew Zonenberg: Fixed typo in coolrunner docs
<openfpga-github>
openfpga/master 1793163 Andrew Zonenberg: Added xptools
<azonenberg>
This is going to be quite the chain of toolling
<azonenberg>
From gp4tchar (characterization driver)
<azonenberg>
i have a USB connection to the greenpak devkit
<azonenberg>
then a TCP connection to GreenpakTimingTest
<azonenberg>
Which has a TCP connection to nocswitch
<azonenberg>
Which has a TCP connection to jtagd
<azonenberg>
Which has a JTAG connection to starshipraider
<azonenberg>
Which has a LVCMOS33 connection to the greenpak devkit
<azonenberg>
This will get a lot simpler once i get a socket server running on starshipraider
<azonenberg>
then i can cut all the middlemen
<rqou>
azonenberg: there's an error here too:
<rqou>
XC2ZIAInput::IBuf{ibuf: 28},
<rqou>
er
<rqou>
FB1 pad 13 (row 2, 12, 28)
<rqou>
FB1 pad 12 (row 10, 16, 31, 12)
<rqou>
12 is there twice
<rqou>
probably should be 39?
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<openfpga-github>
[openfpga] azonenberg pushed 1 new commit to master: https://git.io/vH4yb
<openfpga-github>
openfpga/master 47eba72 Andrew Zonenberg: Continued work on GreenPAK timing characterization
<rqou>
azonenberg: what happened to this?
<rqou>
FB1 pad 13 (row 2, 12, 28)
<rqou>
FB1 pad 12 (row 10, 16, 31, 12)
<rqou>
12 is duplicated
<azonenberg>
rqou: i have it saved
<azonenberg>
just wanted to push the work i did earleir today before bed
<azonenberg>
i was out in the woods looking for two missing kids half the night when i could have been coding
<rqou>
aah
<azonenberg>
i'll get to that in the morning once i'm more awake :p
<rqou>
ok
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<rqou>
hmm, something strange
<rqou>
do unused FFs toggle with GCK0?
<rqou>
that seems like it wastes power unnecessarily
<rqou>
but i don't see anything that can disable taht
<rqou>
wait no they don't toggle obviously
<rqou>
but they will read their garbage inputs and forward them to their outputs
<rqou>
no wait
<rqou>
yeah it seems this does happen
<rqou>
hmm
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<rqou>
hmm the xilinx .jed parser isn't _completely_ scanf-based
<rqou>
it does still have some intelligence
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<rqou>
azonenberg: what happens if i try to use a zia row where i haven't enabled anything at all?
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<rqou>
azonenberg: hmm xilinx actually does seem to have a real jed parser
<rqou>
i think i somehow just messed it up when i was testing before
<rqou>
maybe i forgot the * at the end of the line or something
<rqou>
yeah i messed it up before
<rqou>
except xilinx doesn't support the F field
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<rqou>
they output it but can't actually read it
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<azonenberg>
rqou: So, there is no "havent enabled anything"
<azonenberg>
the all-idle row ties it to a constant value because one of the pass transistors is a pfet instead of a nfet
<azonenberg>
You'd need to invert that bit to turn off ALL pass transistors
<rqou>
but what if I do write 01111111?
<rqou>
what happens?
<azonenberg>
It looks like there's a weak keeper/pull circuit to keep it somewhat stable
<cr1901_modern>
A British politician called Ed Balls accidentally tweeted his name. Because the word "Balls" is funny, it became a meme and national holiday
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<rvense>
harh
<rvense>
there was also the time brett easton ellis tweeted "come over, bring coke"
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