clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<jkiv> Hey all, having issues synthesizing. I'm finding yosys optimizes nearly everything in my project out of existence. Any tips to help figure out why?
<jkiv> (version Yosys 0.7+435 (git sha1 a96c775a, clang 4.0.1-6 -fPIC -Os))
<sorear> the usual cause for that is that it's not connected to I/Os
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<jkiv> If the design passes simulation tests, is that reason enough to believe things are connected to IOs?
<sorear> these two things are unrelated
<ZipCPU> jkiv: Have you tried using the yosys "show" command?
<ZipCPU> Often you can use that to see if particular logic components aren't connected as you might expect.
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<jkiv> @ZipCPU, yeah I've tried that as well as write_verilog, with synth. It's still clobbering everything but a register and some top-level inputs.
<ZipCPU> How big is your project
<ZipCPU> ?
<jkiv> 5 modules, 1500 LoC
<jkiv> Oops, that includes tests
<jkiv> About 700 LoC
<jkiv> I have two large registers in the top-level that are passed down to the lowest-level modules that have constant value.
<jkiv> I remember at one point, if I made those input wires, it had better success as synthesizing the lower-level stuff.
<jkiv> Should I be declaring these constants differently than reg with literal values?
<jkiv> Might be related, or just coincidental
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<ZipCPU> jkiv: Can you share any of what you are doing? I can take a look and see if I see anything if you would like.
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