clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<mithro> This seems pretty cool -> https://github.com/fkling/astexplorer
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<ZipCPU> mattvenn_: Sorry, I was out.
<ZipCPU> The else is necessary.
<ZipCPU> No latch will be inferred without it, though, for the simple reason that this is clocked logic.
<ZipCPU> I see the bug with the "reg phase_err", that should be a wire.
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