clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<vinny> Hi all. Is there a manner to flatten the ports of a module into individual 'pins'
<vinny> I tried the flatten and expose passes, but they didn't seem to work.
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<awygle> vinny: splitnets, maybe?
<awygle> If I understand the question
<vinny> awygle: Thanks. That worked! :-)
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