clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach> ZipCPU: I can't think properly now. For https://i.imgur.com/o29ySQX.png , what do you have in mind regarding https://github.com/promach/UART/blob/development/rtl/Rx/detect_start_bit.v#L57 ?
<ZipCPU> promach: Are you asking me to design your code for you?
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<promach> ZipCPU: I got past that error. I am now facing more assert across each stages of UART transaction
<promach> probably I will leave that to tomorrow
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