clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<ravenexp> what's the best way to extract docstrings from verilog sources?
<ravenexp> there's doxygen-verilog fork, but its output quality is terrible and it crashes in random places
<ravenexp> then there's Verilog::Perl, but it requires some programming
<ravenexp> maybe yosys has some features wrt. meta commant extraction?
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<mattvenn_> ZipCPU - you around? I'm working through the digi pll example and have a question
<mattvenn_> why do you need an else if condition? why not just use else?
<mattvenn_> and might not using the else if result in an unintended latch?
<mattvenn_> (without the else)
<mattvenn_> I also get an error when trying to test your code - sdpll.v:103: error: reg phase_err; cannot be driven by primitives or continuous assignment.
<mattvenn_> I changed it to a reg and use an always block to assign it
<mattvenn_> sorry, it was a reg - I put it in an always block to assign it instead of the assign = in your code
<mattvenn_> gotta go, back on Monday
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