<azonenberg>
Routed the 40GbE diffpairs plus three of the pods. The rightmost two are going to take a more awkward path layer-hopping a bit
<monochroma>
:D
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<azonenberg>
one challenge i'm facing is that the diffpair design rules i use for internal layers don't fit between 1mm pitch vias
<azonenberg>
So i'm likely going to have to push them too close, reducing the impedance below 100 ohms differential, during the fan-out and then jump up to the correct spacing once free of the grid
<azonenberg>
an outer layer pair can fit between vias/balls no problem
<azonenberg>
Also i'm length matching bits within a pod tightly to minimize skew within a group of related signals, but not attempting to match too tightly from pod to pod
<azonenberg>
I'll be using the IDELAYE2 for delay tuning from pod to pod
<azonenberg>
in an effort to get +/- 1 bit of skew across the whole instrment
<azonenberg>
then i still have to do the muxing for the high-speed inputs, the Vref/Vtt supplies, and a bunch of random support stuff like the fpga boot flash
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<_whitenotifier-b>
[scopehal] azonenberg pushed 1 commit to master [+0/-0/±1] https://git.io/JJmXB
<_whitenotifier-b>
[scopehal] azonenberg 63b6d5f - RigolOscilloscope: fixed defaulting to MSO5 protocol when we should have used DS
<_whitenotifier-b>
[scopehal-cmake] azonenberg pushed 1 commit to master [+0/-0/±1] https://git.io/JJmX0
<azonenberg>
The RGMII bus will be annoying, i need to get a dozen or so single ended lines from the southwest corner of the FPGA out to the Ethernet PHY area in the northeast corner
<azonenberg>
there's no good path that doesn't run under a huge number of other stuff :p
<azonenberg>
lain: the fun will be length matching this all, accounting for package delays etc
<lain>
yeah that'll be... fuuuuuun
<azonenberg>
They want me to length match each byte group to better than 5ps vs the associated DQS
<azonenberg>
Meanwhile package skew can be ~150ps
<azonenberg>
although i imaigne within a group it's a lot less, but still
<azonenberg>
also it warns about CK/CK# must arrive after DQ/DQS to each memory component
<azonenberg>
and that i need to account for delay on the DIMM when doing this?
<azonenberg>
is there a jedec spec for skew on a sodimm?
<azonenberg>
I mean i still have a lot more rough layout to do before i can do the fine tuning, but still
<lain>
I was pretty sure sodimm skew is effectively 0
<lain>
but I might be wrong
<lain>
well, what ddr is this? 3?
<azonenberg>
3
<azonenberg>
I thought it was fly by routing
<azonenberg>
so you have huge variations from one side of the dimm to the other?
<lain>
DQ is point to point, address/control is fly by
<azonenberg>
Yes
<azonenberg>
But they say CK/CK# must arrive after DQ/DQS
<azonenberg>
What's the propagation delay for CK vs DQS on the module?
<lain>
hm
<lain>
not sure
<lain>
it might be in the sodimm spec??
<azonenberg>
Can i safely assume every clock-to-chip path is longer than every dqs-to-chip path?
<lain>
ok yeah it's specified in the sodimm jedec pdf
<lain>
4.20.18
<lain>
section "Clock Control and Address/Command Cgroups"
<lain>
Groups*
<azonenberg>
you had that handy>?
<lain>
yeah
<azonenberg>
i just finished download ing it
<lain>
you don't? ;)
<azonenberg>
No
<azonenberg>
well i do now :p
<lain>
although
<lain>
these numbers are length matching and not specified by delay, what the heck
<lain>
I mean they do specify that they compensate for velocity differences, but...
<azonenberg>
Sodimms have a temp sensor?
<lain>
some do
<azonenberg>
what i2c address?
<azonenberg>
this might be a problem, i might have to reassign some addresses :p
<lain>
lol
<lain>
uhhh I forget what jedec doc governs SPD addresses
<lain>
oh it's an annex to the DDR3 stuff
<lain>
I don't think I have it handy, just the ddr4 one
<azonenberg>
So "CTRL to CLK matching"
<azonenberg>
no wait
<azonenberg>
what about byte group to CK?
<azonenberg>
i don't see this specified
<lain>
>The length of the individual byte lanes may vary substantially across the module, with the controller providing timing realignment circuitry.
<lain>
page 31, as of my copy which is release 24, revision 2.8
<Degi>
The controller on the module?
<lain>
I'm beginning to understand why some things only work with some sticks
<azonenberg>
lol
<lain>
Degi: the modules don't have controllers, they're referring to the controller in the host
<Degi>
Oh, that square in the middle that there sometimes is isnt a controller?
<lain>
Degi: correct
<azonenberg>
On RDIMMs? that's just a buffer on the address/control iirc
<Degi>
Oh
<lain>
yep, it's a buffer for registered dimms
<azonenberg>
lain: So looking at "raw card F" for example i see clock routes ranging from 28 to 195 mm
<azonenberg>
And 24 to 30 for DQ/DQS
<azonenberg>
So basically worst case the dimm clock is a tiny bit shorter than byte groups
<azonenberg>
If i add a relatively small amount of skew on the PCB i should be OK
<azonenberg>
you agree with that?
<lain>
azonenberg: agree
<azonenberg>
the MIG docs say that the allowed skew is 0 to 1600 ps
<Degi>
Hmh I think all signals need to be within +- 45 degrees of the clock?
<azonenberg>
so if i add 250ps or so of deliberate delay from clock to longest byte group, i should be OK
<azonenberg>
Degi: the design rules i have say:
<azonenberg>
(UG586 page 187)
<azonenberg>
* Byte group to DQS: +/- 5 ps
<azonenberg>
* Addr/ctrl to CLK: +/- 25 ps
<azonenberg>
CLK to byte group: -0 +1600 ps
<azonenberg>
They also allow you to steal some extra timing margin by using faster RAM. So if I load DDR3 2133 on a -2 speed kintex7 and run the interface at 1600 MT/s, I can get +/- 62ps from DQ to DQS
<azonenberg>
But if i loaded DDR3 1600 i'd only have +/- 31 ps
<azonenberg>
and if i used a -1 speed I'd be down to the +/- 5ps from the original guidelines
<azonenberg>
equally, addr/control to clock skew can go u pto +/- 124ps assumin gi use 2133 rated ram
<azonenberg>
I'm going to try to match tighter than that to allow use of 1866 or 1600 rated ram if possible
<azonenberg>
but it's nice to know i can steal more if need be
<azonenberg>
Anyway i'm not length matching it yet. Just trying to get rough layout
<azonenberg>
As you can see i'm a long way from done :p
<azonenberg>
I started on the "easy" corner where i had two sides of the chip to fan out the bank
<lain>
woo
<azonenberg>
and it was oriented with the wide axis parallel to the side of the chip
<azonenberg>
The middle bank is address/control and less full
<azonenberg>
but the left one is a nearly full DQ bank and has a full bank of LVDS inputs to the left
<azonenberg>
So that will be fun to fan out
<azonenberg>
I think before i do more ram i want to finish the right side of the FPGA though. I need to do all of the muxes for the SERDES LA inputs, then place a bunch of bulk decoupling caps etc
<azonenberg>
And i have all of the inputs from pods 10 and 11 that need to sneak into some already-full banks in the bottom center
<azonenberg>
will probably have to move some of these to other layers to space them out more
<lain>
ugh I'm going to use 0201's for the smol capacitors on this design
<lain>
without ViP it's too hard to fit them all close to the relevant power balls
<lain>
0.8mm pitch BGA
<lain>
honestly even with ViP, 0402 is kinda big for 0.8mm pitch
<lain>
but 0402 perfectly lines up with 1.0mm pitch BGA!
<azonenberg>
yeah i love it
<azonenberg>
luckily almost all big xilinx parts are 1mm
<azonenberg>
aaand just confirmed MIG likes the addr/ctrl pinout
<azonenberg>
So that's 2/3 of the dram banks routed now, not bad
<azonenberg>
of course none of them are length matched yet, that's the hard part :p
<azonenberg>
Managed to do addr/control entirely on two layers so i have plenty of room to move them to internal layers to space them out and reduce xtalk