sb0 changed the topic of #m-labs to: https://m-labs.hk :: Logs http://irclog.whitequark.org/m-labs :: Due to spam bots, only registered users can talk. See: https://freenode.net/kb/answer/registration
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<sb0> should we just do ARTIQ ASICs?
<sb0> that should solve the execution speed issues for good
<sb0> plus, we can put a large SRAM in there to avoid the poor real-time properties of DRAM
<cr1901_modern> The price... isn't horrible?
<sb0> not that much. the tools and intellectual poverty are worse than vivado, though. so the time spent taking out the trash will certainly drive up costs.
<cr1901_modern> "intellectual poverty" freudian slip?
<GitHub-m-labs> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/migen/commit/ba633645c2fef6de820538aace458646462207c5
<GitHub-m-labs> migen/master ba63364 William D. Jones: platforms/ice40_hx8k_b_evn: Add pins for spiflash io.
<sb0> usually abbreviated as "IP"
<cr1901_modern> yes I know... I think you meant Intellectual _Property_
<cr1901_modern> and I made a bad joke
<bb-m-labs> build #318 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/318
<GitHub-m-labs> [artiq] sbourdeauducq created switching125 (+2 new commits): https://github.com/m-labs/artiq/compare/969a305c5a2d^...9f96b6bcda7d
<GitHub-m-labs> artiq/switching125 9f96b6b Sebastien Bourdeauducq: kasli: use 125MHz DRTIO freq for testing
<GitHub-m-labs> artiq/switching125 969a305 Sebastien Bourdeauducq: Merge branch 'master' into switching125
<sb0> hartytp: ^ no crash with the code above either. things seem to be working.
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<sb0> hartytp: and if you get sdram issues, revert the last commit in misoc that lowers the frequency. i did that while developing switching to get this pesky bug out of the way, and it met timing every time.
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<GitHub-m-labs> [artiq] hartytp commented on issue #1166: Reproduced in a fresh conda environment with a current master, now clocking at 100MHz. Binaries are [here](https://drive.google.com/open?id=1_h-E_fdQIOmMpUdifZFKY9qnXg2y_Mep), timing is met.... https://github.com/m-labs/artiq/issues/1166#issuecomment-426971243
<GitHub-m-labs> [artiq] hartytp commented on issue #1166: Looking at all channels on a fast scope. Using an ac-coupled TCM2-43X+ and a 50Ohm scope. Channel numbers refer to the physical ordering of the SMPs, with the ones nearest the SATA connectors being 7 (I recall the mapping between SMPs and DAC channels being somewhat screwy).... https://github.com/m-labs/artiq/issues/1166#issuecomment-426974385
<GitHub-m-labs> [artiq] hartytp commented on issue #1166: So we have these odd glitches and channels 3/7 show some odd curvature...... https://github.com/m-labs/artiq/issues/1166#issuecomment-426975813
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<GitHub-m-labs> [artiq] jordens commented on issue #1166: The "odd curvature" (assuming you are talking about the low frequency deviation from the sawtooth) on 1,3,5,7 is your balun AFAICT. Do they worry you?... https://github.com/m-labs/artiq/issues/1166#issuecomment-427009664
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<GitHub-m-labs> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/migen/commit/1e114c76fa1126f0fe2523ec500c70cb43efd288
<GitHub-m-labs> migen/master 1e114c7 N. Engelhardt: add a print to show user context when an exception is raised while evaluating a generator yield statement in simulation
<bb-m-labs> build #319 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/319
<sb0> anyone used urukul 1.3? I get "PLL lock timeout"
<sb0> trying to use mmcx and the settings used to work with the previous version
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<sb0> well the cpld isn't driving MMMX_OSCn_SEL and OSC_ENn properly - those are routed to spi - so that's not going to work
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<sb0> were those cards tested...?
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<GitHub-m-labs> [artiq] sbourdeauducq pushed 2 new commits to master: https://github.com/m-labs/artiq/compare/d0ee2c2955e2...86fe6b05949e
<GitHub-m-labs> artiq/master 86fe6b0 Sebastien Bourdeauducq: kasli: add NUDT variant
<GitHub-m-labs> artiq/master a89bd6b Sebastien Bourdeauducq: kasli: swap Urukul EEMs for Tester...
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<hartytp> sb0: needs new cpld gateware
<hartytp> I will write it, but was waiting for hw to arrive
<hartytp> just got it, so will do that tomorrow
<hartytp> it's a trivial change
<bb-m-labs> build #1888 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1888
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<bb-m-labs> build #1889 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1889
<bb-m-labs> build #2618 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2618
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<GitHub-m-labs> [artiq] cjbe opened issue #1167: Artiq performance on Zynq https://github.com/m-labs/artiq/issues/1167
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<GitHub-m-labs> [artiq] klickverbot commented on issue #1167: (EH doesn't support unhandled exceptions yet; I'll add that and pretty up the code if we want ARM support in upstream.) https://github.com/m-labs/artiq/issues/1167#issuecomment-427186352
<GitHub-m-labs> [artiq] klickverbot commented on issue #1167: (The EH code doesn't handle uncaught exceptions yet; I'll add that and pretty up the code if we want ARM support in upstream.) https://github.com/m-labs/artiq/issues/1167#issuecomment-427186352
<GitHub-m-labs> [artiq] cjbe commented on issue #1167: Some implementation notes:... https://github.com/m-labs/artiq/issues/1167#issuecomment-427188287
<GitHub-m-labs> [artiq] klickverbot commented on issue #1167: (This could be exposed to user code as a `with` context which modifies the underflow semantics so errors are read back in a blocking fashion only once when the block is left.) https://github.com/m-labs/artiq/issues/1167#issuecomment-427189218
<GitHub-m-labs> [artiq] gkasprow commented on issue #1167: We had some discussion with @hartytp a few weeks ago. We even looked at the chips and packages and XC7Z030-2FFG676I seem to be good choice - it has enough pins to serve 12EEMs and 4 transceivers. https://github.com/m-labs/artiq/issues/1167#issuecomment-427190553
<GitHub-m-labs> [artiq] gkasprow commented on issue #1167: ZynQ US+ has two additional real time R5 cores. Maybe they gain better performance in such use case ?... https://github.com/m-labs/artiq/issues/1167#issuecomment-427191232
<GitHub-m-labs> [artiq] cjbe commented on issue #1167: The XC7Z030-2FFG676I looks nice for a Kasli-type EEM controller:... https://github.com/m-labs/artiq/issues/1167#issuecomment-427194529
<GitHub-m-labs> [artiq] hartytp commented on issue #1167: > Max CPU clock 866 MHz... https://github.com/m-labs/artiq/issues/1167#issuecomment-427195676
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1167: > So, there is a modest RTIO event speedup, and a really significant computational / FP speedup.... https://github.com/m-labs/artiq/issues/1167#issuecomment-427206008