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<GitHub-m-labs> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/migen/commit/d3b875b46eee4d34e093e63cd769bdfaae0da3df
<GitHub-m-labs> migen/master d3b875b Piotr Esden-Tempski: Fixed on board green led pin number. Added "multi" led.
<bb-m-labs> build #317 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/317
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1164: @jordens Can you look into this? https://github.com/m-labs/artiq/issues/1164#issuecomment-426116629
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1164: @jbqubit Wrong ref_period? https://github.com/m-labs/artiq/issues/1164#issuecomment-426116890
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1164: @jbqubit Wrong ref_period? It seems that the SAWG may be producing the correct output, except that the steps are too short. https://github.com/m-labs/artiq/issues/1164#issuecomment-426116890
<GitHub-m-labs> [artiq] jbqubit commented on issue #1164: Agreed pulses were too short. Works fine with longer pulses. https://github.com/m-labs/artiq/issues/1164#issuecomment-426124045
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<hartytp> sb0: thinking about Sayma PLLs/dividers, what about switching the HMC830 to something like the ADF4371?
<hartytp> afaict, that has a divider that is inside the feedback path, which makes life much easier
<hartytp> also, it's the same PLL that will be used on Mirny, so we can share some code between Sayma and Mirny (and MixMod)
<hartytp> well, both code and hardware development costs
<hartytp> sb0: ping
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<hartytp> sb0: seems to work!
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<GitHub-m-labs> [artiq] hartytp closed issue #1083: Sayma: SYSREF alignment problems https://github.com/m-labs/artiq/issues/1083
<07IAAGFZ3> [artiq] hartytp closed issue #698: Sayma "calibration" ADC support https://github.com/m-labs/artiq/issues/698
<7GHAACDMC> [artiq] hartytp commented on issue #698: Closing this, since we've provisionally agreed to scrap this ADC in v2.0 (although, we may add I2C ADCs to the afe mezzanines, but that should probably included as part of the support issue for those AFE cards) https://github.com/m-labs/artiq/issues/698#issuecomment-426264298
<GitHub-m-labs> [artiq] hartytp closed issue #921: serial over IP for Sayma https://github.com/m-labs/artiq/issues/921
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<hartytp> sb0: how fast can we run the transceiver refclk input? Can we drive it at 2.4GHz?
<sb0> or maybe double that if you use the input divider, the datasheet isn't clear
<hartytp> ack. well, I'm not sure if the JESD reset CDC is a red herring or not, but it's my first suspicion. Anyway, this will all be much easier in Sayma v2.0 when we have a chance to rethink the clocking
<hartytp> hmmover the past 16 restarts of the FPGA I've had two cases where the RF phase jumped by approx 8.3ns so 5 cycles of the 600MHz, and one case where it was miles off
<sb0> hartytp: no problem re. ADF4371 noise?
<hartytp> from a skim over the data sheet, I don't think so, but it's on my list of things to think about before we make a final decision on that. The issue was just a starting point for the conversation, not a firm recommendation of pns
<hartytp> sb0: are you likely to have time for a code review any time soon, or should I take the appaus to pieces and leave this for Sayma v2.0?
<sb0> hartytp: not sure if I'll have time, but I don't recommend dismantling it either, as most sayma problems consist almost entirely of debugging
<hartytp> well, I won't completely disassemble it, but it's a fragile mess sprawling over a desk and I can't leave it like that.
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1155: @jordens ping https://github.com/m-labs/artiq/issues/1155#issuecomment-426298738
<hartytp> as I said though, I think I've done enough to enable us to make informed decisions about hw for the next revision and enough that I'm no longer the correct person to do this kind of work (should be someone who understands the gateware better)
<sb0> we can probably multiply the time you spent already by 10 or so, to estimate how long it would take on 2.0 including fixing this bug...
<hartytp> what do you mean?
<hartytp> we now have a good sysref that meets s/h at the FPGA reliably. there are no 2.4GHz ambiguities, just what looks like a jesd framing issue (600MHz issues)
<sb0> well ok, then at least some hmc7043 insanity seems out of the equation, but there's more to come
<hartytp> we've gone from a blank slate, including uncertainty about the delay lines, etc and bugs in the DAC itself, to what appears to be a gateware issue.
<sb0> why is this not a DAC bug? we don't know...
<sb0> are the DACs synced with each other?
<GitHub-m-labs> [artiq] jordens commented on issue #1155: Waiting for another kasli. https://github.com/m-labs/artiq/issues/1155#issuecomment-426305968
<GitHub-m-labs> [artiq] jordens commented on issue #1155: If you have two, you can test it yourself. https://github.com/m-labs/artiq/issues/1155#issuecomment-426306045
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<hartytp> sb0: could be a dac bug, but somehow that seems less likely than a jesd bug
<hartytp> sb0: i haven't checked if the dacs are synchronised with each other. the rework to inject an external sysref is a complete pita and I don't have time to do it again
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<hartytp> sb0: question about JESD...if we synchronise the DAC by sending in a SYSREF pulse and then, later on, send in another SYSREF pulse with a different phase to resynchronise the DAC to a different phase, what happens?
<hartytp> in particular, is some data lost during the resync?
<hartytp> my init sequence rearms the DAC sync engine in case of errors, but does not reset the FPGA JESD core. Could that be an issue, or could that lead to lost samples?
<hartytp> well, one way to find out I guess
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