sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<cr1901_modern>
whitequark: I assume you have multiple Clang/LLVM installations on the same machine. Since LLVM includes all archs that have been merged upstream via one set of user binaries, what's your preferred method to ensure two installations don't conflict w/ each other?
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<mithro>
so, how would you go about testing the spiflash module is working on a board?
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<sb0>
mithro, on both pipistrello and kc705
<mithro>
sb0: I'm trying to make loading the firmware from the spiflash on my design work and I'm having trouble getting it working.
<mithro>
The spiflash is mapped into a memory region right? But at the start of the spiflash is the gateware, so we need to skip over that when we load and write the firmware
<rjo>
and bios
<mithro>
rjo: I'm still currently trying to keep the bios embedded in the gateware?
<rjo>
ack
<mithro>
How would the bios booting from spiflash work? Does the controller have some type of "offset" support which would make a different region of the flash appear at addr 0x00000?
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<mithro>
rjo: is that what the "dummy" argument does?
<sb0>
you can select the CPU reset address
<rjo>
the dummy argument does dummy spi cycles.
<mithro>
actually I had an idea - I should write know values to the spiflash and use the bios mr command to try and read them
<rjo>
your bitstream has know values.
<mithro>
The spiflash is read only, right? (You have to use the bitbanging interface to write to it...)
<rjo>
yes
<mithro>
hrm, using mr to read from that address doesn't seem to work....
<mithro>
bblr
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<sb0>
cr1901_modern, Since the API change in MiSoC, users no longer
<sb0>
have the ability to override this behavior when building a target. << what option is missing exactly?
<sb0>
was it there before?
<GitHub103>
[migen] sbourdeauducq pushed 1 new commit to master: https://git.io/vVF69
<GitHub103>
migen/master c44664d William D. Jones: xilinx/ise: source settings files by default on Windows
<mithro>
So, the data being "read" from the spiflash doesn't really resemble the data I think I have written to the spiflash, any idea on how to debug what is going on?
<rjo>
anything. data width, read command, dummy cycles.
<rjo>
endianess
<mithro>
rjo: Yeah - I'm trying to drop the spi flash back down to 1x mode and then reading the contents - I know the contents should be "FL<16bit number>" where the number increases by 1
<mithro>
I'm wondering if I have dq's around the wrong way when using the 2x mode
<mithro>
openocd seems to be able to read/write the SPI flash fine using the proxy, so I'm wondering if it is worth trying to just write a small extension to the bios to read the SPI flash ID to confirm that I have things like the pins right
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<cr1901_modern>
sb0: The ability to add the option "-Ob source True" on the command line is missing ever since MiSoC switched from using from ussing make.py to having the argument parsing built into the targets
<GitHub3>
[artiq] sbourdeauducq pushed 4 new commits to master: https://git.io/vVFHr
<cr1901_modern>
sb0: Not with my submitted patch which makes source default to True. But before this point, I've always had to set source=True when building anything with MiSoC, old or new API.
<cr1901_modern>
Hell, I have to set source=True in general when using Migen b/c Xilinx tools are not on my path (nor would I expect them to be)
<rjo>
"originally dubbed AEHOO (All Encompassing Hierarchical Object Oriented format) began in 1987 ... NASA investigated 15 different file formats ... HDF was selected".
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<GitHub187>
[artiq] jordens pushed 1 new commit to release-1: https://git.io/vVbZl
<GitHub187>
artiq/release-1 6552aa4 Robert Jordens: test: set inputs to input(), should close #383