sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<cr1901_modern> whitequark: I assume you have multiple Clang/LLVM installations on the same machine. Since LLVM includes all archs that have been merged upstream via one set of user binaries, what's your preferred method to ensure two installations don't conflict w/ each other?
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<mithro> so, how would you go about testing the spiflash module is working on a board?
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<mithro> sb0: Probably not helpful to you, but I came across http://www.ohwr.org/projects/conv-ttl-blo-gw/wiki/xil_multiboot today
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<mithro> sb0: are you using the spiflash on the pipistrello in artiq?
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<sb0> mithro, on both pipistrello and kc705
<mithro> sb0: I'm trying to make loading the firmware from the spiflash on my design work and I'm having trouble getting it working.
<mithro> The spiflash is mapped into a memory region right? But at the start of the spiflash is the gateware, so we need to skip over that when we load and write the firmware
<rjo> and bios
<mithro> rjo: I'm still currently trying to keep the bios embedded in the gateware?
<rjo> ack
<mithro> How would the bios booting from spiflash work? Does the controller have some type of "offset" support which would make a different region of the flash appear at addr 0x00000?
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<mithro> rjo: is that what the "dummy" argument does?
<sb0> you can select the CPU reset address
<rjo> the dummy argument does dummy spi cycles.
<mithro> actually I had an idea - I should write know values to the spiflash and use the bios mr command to try and read them
<rjo> your bitstream has know values.
<mithro> The spiflash is read only, right? (You have to use the bitbanging interface to write to it...)
<rjo> yes
<mithro> hrm, using mr to read from that address doesn't seem to work....
<mithro> bblr
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<sb0> cr1901_modern, Since the API change in MiSoC, users no longer
<sb0> have the ability to override this behavior when building a target. << what option is missing exactly?
<sb0> was it there before?
<GitHub103> [migen] sbourdeauducq pushed 1 new commit to master: https://git.io/vVF69
<GitHub103> migen/master c44664d William D. Jones: xilinx/ise: source settings files by default on Windows
<bb-m-labs> build #70 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/70
<bb-m-labs> build #94 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/94
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<bb-m-labs> build #332 of artiq-kc705-nist_clock is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-kc705-nist_clock/builds/332
<bb-m-labs> build #115 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/115
<bb-m-labs> build #591 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/591
<mithro> So, the data being "read" from the spiflash doesn't really resemble the data I think I have written to the spiflash, any idea on how to debug what is going on?
<rjo> anything. data width, read command, dummy cycles.
<rjo> endianess
<mithro> rjo: Yeah - I'm trying to drop the spi flash back down to 1x mode and then reading the contents - I know the contents should be "FL<16bit number>" where the number increases by 1
<mithro> I'm wondering if I have dq's around the wrong way when using the 2x mode
<mithro> openocd seems to be able to read/write the SPI flash fine using the proxy, so I'm wondering if it is worth trying to just write a small extension to the bios to read the SPI flash ID to confirm that I have things like the pins right
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<cr1901_modern> sb0: The ability to add the option "-Ob source True" on the command line is missing ever since MiSoC switched from using from ussing make.py to having the argument parsing built into the targets
<GitHub3> [artiq] sbourdeauducq pushed 4 new commits to master: https://git.io/vVFHr
<GitHub3> artiq/master 0cca2bb Sebastien Bourdeauducq: artiq_run: style
<GitHub3> artiq/master 3c70bc4 Sebastien Bourdeauducq: master/worker_db: add pause_devices and resume_devices
<GitHub3> artiq/master 437b37b Sebastien Bourdeauducq: master/worker: pause/resume devices
<cr1901_modern> sb0: Furthermore, there's no way to insert source=True at all into the new MiSoC. See kwargs of the highlighted: https://github.com/m-labs/misoc/blob/master/misoc/integration/builder.py#L151-L156
<sb0> do you need that?
<bb-m-labs> build #333 of artiq-kc705-nist_clock is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-kc705-nist_clock/builds/333
<cr1901_modern> sb0: Not with my submitted patch which makes source default to True. But before this point, I've always had to set source=True when building anything with MiSoC, old or new API.
<cr1901_modern> Hell, I have to set source=True in general when using Migen b/c Xilinx tools are not on my path (nor would I expect them to be)
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<bb-m-labs> build #116 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/116
<bb-m-labs> build #592 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/592
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<whitequark> cr1901_modern: well Debian suffixes the LLVMs with a version
<whitequark> otherwise, I simply don't install them, LLVM builts its tools with -Wl,-rpath that allows them to run from anywhere on the filesystem
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<rjo> "from . import h5a, h5d, h5ds, h5f, h5fd, h5g, h5r, h5s, h5t, h5p, h5z": alphabet soup
<whitequark> wtf is that file format
<rjo> it's a classic
<cr1901_modern> whitequark: Ack/noted, thanks!
<rjo> "originally dubbed AEHOO (All Encompassing Hierarchical Object Oriented format) began in 1987 ... NASA investigated 15 different file formats ... HDF was selected".
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<GitHub187> [artiq] jordens pushed 1 new commit to release-1: https://git.io/vVbZl
<GitHub187> artiq/release-1 6552aa4 Robert Jordens: test: set inputs to input(), should close #383
<GitHub82> [artiq] jordens pushed 1 new commit to master: https://git.io/vVbZ8
<GitHub82> artiq/master d42ef46 Robert Jordens: test: set inputs to input(), should close #383
<bb-m-labs> build #334 of artiq-kc705-nist_clock is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-kc705-nist_clock/builds/334
<bb-m-labs> build #117 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/117
<bb-m-labs> build #593 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/593
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<GitHub94> [artiq] jordens pushed 1 new commit to release-1: https://git.io/vVbVT
<GitHub94> artiq/release-1 90876e0 Robert Jordens: examples: move pdq2 frame selects away from TTLInOut ttl3
<GitHub167> [artiq] jordens pushed 1 new commit to master: https://git.io/vVbVI
<GitHub167> artiq/master 5788c02 Robert Jordens: examples: move pdq2 frame selects away from TTLInOut ttl3
<bb-m-labs> build #335 of artiq-kc705-nist_clock is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-kc705-nist_clock/builds/335
<bb-m-labs> build #594 of artiq is complete: Failure [failed python_unittest_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/594 blamelist: Robert Jordens <rj@m-labs.hk>
<mithro> okay, looks like I've gotten the flash working on the Atlys board, but still nothing on the minispartan6
<mithro> Changing the "dummy=xxx" value seems to change the values read....
<mithro> I think the key might be "MXIC IC will enable output an entire cycle in advance compare with other compatible vendor's spec"
<mithro> Which means dummy actually needs to be 7 or 8 on this part....
<mithro> okay, a dummy of 0 is giving me the right output but a byte offset
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<cr1901_modern> sb0: What Qt API did you use to enable multiple windows inside a larger one in artiq (for my future reference)
<sb0> QMdiArea/QMdiWindow
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<sb0> _florent_, mithro: are you still running the ddr3 out of specs (clock is too slow) on the opsis?
<_florent_> sb0: yes... I should look at that
<sb0> what would be required to operate at 1Gbps like on the kc705?
<sb0> are the uncalibrated iodelays even stable enough to permit that?
<sb0> the spartan6 iodelays should also be renamed iojitter
<sb0> whitequark, can i start merging your compiler changes into release-1?
<whitequark> sure
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<_florent_> sb0: we are using the DDR2 phy in quarter rate, to run at 1Gbps we could try with something similar to the kc705
<_florent_> sb0: but indeed I'm not sure it will work with the s6 iodelays...
<sb0> doesn't the ddr2 also require iodelays?
<sb0> oh, you are just using the ddr2 phy with ddr3.
<_florent_> sb0: yes, with a wrapper around it for quarter rate: https://github.com/m-labs/misoc/blob/master/misoc/cores/sdram_phy/s6ddrphy.py#L400
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<mithro> sb0: need more bandwidth?
<mithro> sb0: do you do training courses at all? I know you did a bit of lecturing?
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