02:04 <whitequark> cr1901_modern: normal python does not need to specialize methods for different arguments

02:07 <cr1901_modern> whitequark: I'm sorry, are you willing to elaborate? I'm assuming you have to specialize methods for different arguments b/c of the constraints that ARTIQ puts on the code. I still don't see why specializing methods for different classes based on inheritance is that much tougher.

02:09 <whitequark> the compiler doesn't know anything about inheritance, nor even it treats the self argument as something special

02:10 <cr1901_modern> Perhaps I should review how Python implements inheritance internally and see if I still have questions

02:15 <cr1901_modern> whitequark: In NORMAL Python (not your compiler), is self treated specially?

03:00 <whitequark> no

08:36 <sb0> cr1901_modern, just ask away...

12:59 <sb0> whitequark, you may like such a device https://www.yumpu.com/en/document/view/24150177/hwg-wld-water-leak-detector

13:04 <whitequark> sb0: why? do I have water leak problems?

13:06 <sb0> could be an extra safety that shuts down the chiller if a leak appears

13:06 <whitequark> why would a leak appear?

13:07 <sb0> that's not an unusual problem in watercooling systems

13:07 <whitequark> well, I don't really see that happening with correctly sized hose and fittings

13:07 <whitequark> (which, amusingly, is hard, I've seen more than one commercial system with blatantly wrong diameters)

13:08 <whitequark> but if you'd like to be very certain, we can put collets on every connection.

13:08 <whitequark> I have enough for all of them

13:10 <whitequark> the problem with that device is what does it do when a hose has condensate on it?

13:11 <whitequark> sure, condensate means that the system is tuned improperly (there shouldn't be condensate *inside* the pump either) but it's fail-deadly

13:11 <whitequark> it turns off the chiller and the pump cooks

13:18 <sb0> yeah, well, turn off the rest as well

13:21 <whitequark> so that means shutting down turbopump at 100% speed

13:21 <whitequark> just the heater, perhaps, viable. I still vote for collets

15:25 <mithro> what kintex based board are you guys using?

15:29 <rjo> kc705

15:32 <mithro> how "fast" do you run the DDR3 on that?

15:35 <sb0> 1 Gbps/pin

15:35 <sb0> DDR3 has a minimum clock frequency

15:36 <sb0> meeting it on the spartan6 with its broken iodelays and without the magic undocumented mcb components may be challenging.

15:38 <mithro> sb0: 1 Gbps/pin means a 500MHz frequency with DDR?

15:38 <sb0> yes

15:38 <sb0> the mcb uses special circuitry for sampling data, which AFAICT cannot be decoupled from the hardened memory controller logic

15:40 <sb0> in addition to some other undocumented but simpler IOB features

15:42 <sb0> it's a pretty stupid design and it would have been much better if they simply exposed DDR3-compatible data capture/output logic to the fabric

17:08 <GitHub9> [artiq] jordens pushed 7 new commits to master: https://git.io/vrqNj

17:08 <GitHub9> artiq/master cd13045 Robert Jordens: browser: analyze stubs

17:08 <GitHub9> artiq/master 5d58258 Robert Jordens: examples: reconstruct scans when analyze()ing HDF5 files

17:08 <GitHub9> artiq/master 2a5eaea Robert Jordens: flopping_f_simulation: use ufuncs in model()

17:21 <bb-m-labs> build #418 of artiq-kc705-nist_clock is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-kc705-nist_clock/builds/418

17:27 <GitHub160> [artiq] jordens pushed 1 new commit to master: https://git.io/vrqhm

17:27 <GitHub160> artiq/master 260390b Robert Jordens: browser: set objectName for toolbar

17:27 <bb-m-labs> build #174 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/174

17:29 <bb-m-labs> build #684 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/684

17:41 <bb-m-labs> build #419 of artiq-kc705-nist_clock is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-kc705-nist_clock/builds/419

17:46 <bb-m-labs> build #175 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/175

17:47 <bb-m-labs> build #685 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/685

20:24 <cr1901_modern> sb0: Why is Xilinx optimizing out all my sequential logic here https://gist.github.com/cr1901/e9ed9ba9e7cf8c791a0d0545125a36e4

20:25 <cr1901_modern> Well I know the answer, but it doesn't make sense: I manually defined the sys clock domain, and made sure to connect it at the top level

20:26 <cr1901_modern> This is a minimal example of course; the real design has multiple clock domains, so I don't have a choice but to manually define them.