sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0>
_florent_, do you know how sane the default values of GTXE2_CHANNEL parameters are? e.g. if you disable channel bonding and rx clock correction, can you completely omit the corresponding parameters, or will vivado mess things up?
<sb0>
actually that's easy to find out, the default values have been spared by their idiotic secureip. i don't even need to decrypt that...
<cr1901_modern1>
How long would it take to decrypt :P?
<sb0>
the longer step is installing modelsim
<sb0>
then it'll pass the cleartext to memcpy()
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<whitequark>
sb0: the hoses did not leak
<whitequark>
however, the hoses and the pump did condense a massive amount of water, so there's that
<whitequark>
I should probably like, never set it below 25°C
<whitequark>
higher efficiency, too
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<GitHub138>
artiq/master f1747b5 Robert Jordens: browser: only load args from first file
<GitHub138>
[artiq] jordens pushed 3 new commits to master: https://git.io/vrZIE
<GitHub138>
artiq/master ecdbf2a Robert Jordens: browser: wire up activate in list
<GitHub138>
artiq/master 8bff807 Robert Jordens: browser: clean up
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<mumptai>
hi
<rjo>
howdy
<mumptai>
is there a way to use a vhdl ipcore with migen based toplevel?
<rjo>
yes.
<mumptai>
verilog wrapper?
<rjo>
i would think just an Instance() and then let the toolchain figure out how to link them.
<mumptai>
basically use the synthesis tools dual-language interface
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<rjo>
yes.
<mumptai>
i'm not familiar wih the "internel" flow of migen
<mumptai>
-e+a
<mumptai>
i guess i also have to tell migen what interface to exepct? and possibly expand my vdl records into signals and signal-vectors?
<rjo>
towards the toolchain migen just looks like verilog. and it will feed other vhdl/verilog files to the toolchain as well. Platform.add_source()