<sb0>
nothing handles it and designs don't do it. why should they?
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<cr1901_modern>
sb0: They shouldn't. But if they did (by accident), would the platform tools fail gracefully, spit out a difficult-to-debug error, or would they work? I'm not claiming my logic makes sense, that was just my thought process :P.
<sb0>
"difficult" to debug error, I think
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<cr1901_modern>
sb0: Do you suggest that I simply silently discard attempts to assign a second constraint to the same clock signal?
<sb0>
other platforms error at some point
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<cr1901_modern>
Then I'll just raise a ConstraintError, since Icestorm can't actually accept multiple clock constraints right now, and arachne-pnr won't know what to do with constraints added by add_platform_constraint.
<cr1901_modern>
Works for you?
<cr1901_modern>
sb0: ^^ oops
<sb0>
k
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<sb0>
rjo, by the way, Joe spoke of the possibility to output two tones at the same time with the Sayma signal generator
<sb0>
this might increase FPGA resource requirements
<rjo>
sb0: already done. see my e-mail with the proof of concept.
<sb0>
rjo, so the 325t can do it?
<rjo>
yes. but i don't know whether that proposed design makes joe happy. i guess he did not read that mail.