sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<whitequark> sb0: RS says they despatched the gauge components yesterdya...
<whitequark> two days ago even
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<whitequark> sb0: I got your dirty pcbs
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<sb0> there is no xe command installed and packages.debian.org cannot find it.
<sb0> ah, it's in wheezy, xcp-xe
<sb0> but I guess we're not using XCP. and most xen instructions online are for xe.
<sb0> oh. you just need to set mtu on all interfaces, and then you can set it on xenbr0.
<sb0> bah. then the router won't support jumbo frames. i guess i'll just disconnect the kc705 and connect it directly to my laptop for tests...
<sb0> _florent_, why do you round buffer_depth to a power of 2?
<sb0> _florent_, where is your 1532 MTU coming from? shouldn't it be 1530? https://en.wikipedia.org/wiki/Ethernet_frame#Structure
<sb0> or 1522 if you do preamble in gateware
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<whitequark> sb0: xe? no. nononono. no xcp no xe
<whitequark> we only use xl
<whitequark> regarding the router, you can just log in to openwrt
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<sb0> yes, this is how I know it doesn't work
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<whitequark> sb0: at least the filament part works, extremely well: on all range of currents
<whitequark> sb0: please order this: http://hken.rs-online.com/web/p/products/3377088/, I cannot do it right now
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<sb0> whitequark, done
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<_florent_> sb0: we could probably remove the rounding to a power of two on buffer_depth and let the synthesis tool do it
<_florent_> sb0: I don't rembember for the 1532 MTU, but it seems you are right, I'll fix that
<GitHub139> [misoc] enjoy-digital pushed 1 new commit to master: https://git.io/vwwrj
<GitHub139> misoc/master 47da496 Florent Kermarrec: cores/liteeth_mini/common: fix eth_mtu (1530 bytes)
<bb-m-labs> build #96 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/96
<sb0> _florent_, it should be 9000-something for GbE (jumbo frames)...
<sb0> what is the intended behavior of the core when receiving a jumbo frame?
<_florent_> we should maybe make the jumbo frame support optional (to avoid using too much memory when this is not needed)
<sb0> and I think the synthesizers can do non-power-of-two block RAMs.
<bb-m-labs> build #378 of artiq-kc705-nist_clock is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-kc705-nist_clock/builds/378
<sb0> _florent_, we don't really need jumbo frames, but liteeth/lwip should behave correctly when receiving them, which is not the case right now
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<sb0> so either liteeth can fully receive jumbo frames and lwip can grok them, or liteeth should have a well-defined behavior and the lwip driver can detect jumbo frames and do the right thing (it seems send back icmp 3)
<sb0> sending back icmp requires liteeth to retrieve and store the beginning of the frame
<_florent_> ok, then we could try to increase eth_mtu in the gateware, and also adapt the driver: https://github.com/m-labs/artiq/blob/master/artiq/runtime/liblwip/liteethif.c#L39
<sb0> I think the pbuf size needs to be increased as well?
<bb-m-labs> build #150 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/150
<_florent_> yes we'll probably have to adapt lwipopts.h
<sb0> if the block ram isn't padded to a power of 2, the savings become substantial
<bb-m-labs> build #639 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/639
<sb0> afaik block rams of arbitrary depth work just fine
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<rjo> sb0: no. xilinx doc says somewhere they can only infer power of two bram.
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<sb0> http://qsit.weebly.com/ Hong Kong Workshop on Quantum Information and Foundations
<sb0> next week
<sb0> rjo, http://www.xilinx.com/support/answers/33474.html suggests it works, but not optimally
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<rjo> when i tried it it just took the next larger power of two.
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