03:28 <sb0> whitequark, http://www.vk2zay.net/article/251

03:36 <sb0> all the pre-built ones i've found on taobao so far are from keithley and of course expensive

03:39 <sb0> ah, found one. https://item.taobao.com/item.htm?id=528167429673

06:11 <whitequark> 1CNY

06:11 <whitequark> that means custom usually

06:11 <whitequark> well try it...

06:19 <sb0> it's expensive as well

06:19 <sb0> 18000 RMB

06:20 <sb0> op-amp hack it is, then

06:21 <sb0> microwave oven caps OTOH are dirt cheap. a couple RMB a piece...

06:26 <sb0> 1uF 2100V

06:54 <whitequark> yeah, opamp hack sounds good to me

06:54 <whitequark> and I'm quite sure we can improve it a lot by making a proper instrumentation amplifier circuit

06:55 <whitequark> that is, if it's not satisfying

06:55 <whitequark> btw, RS has delivered a lot of stuff

07:13 <sb0> http://www.eetindia.co.in/STATIC/PDF/201212/EEIOL_2013JAN04_AMP_PL_EMS_AN_01.pdf?SOURCES=DOWNLOAD

07:14 <sb0> it seems there is some way to do phase detection with the ISERDES on 7-series

07:14 <sb0> the "double nibble detect" sounds like a gross and unreliable hack

08:09 <sb0> anyway, the interesting features are 1) the IBUFDS_DIFF_OUT primitive that can be used to feed to two ISERDES in the same IOB 2) those two ISERDES can use opposite edges of the clock 3) the serdes-to-serdes skew should be matched well enough for a phase detector, which has similar timing constraints as this DDR sampling example

08:10 <sb0> the only problematic point is whether IDELAY can be used with IBUFDS_DIFF_OUT

08:10 <sb0> in case it can't, we can always change the phase of the clock instead, if there is no unknown data-to-data skew to compensate

08:34 <GitHub66> [artiq] sbourdeauducq pushed 1 new commit to master: https://git.io/vw8Ab

08:34 <GitHub66> artiq/master 3cfef42 Sebastien Bourdeauducq: frontend: upper-case positional arguments in help messages

08:44 <sb0> pulse rate to 600ns?

08:44 <sb0> whitequark, isn't that the event rate?

08:44 <sb0> and pulse rate is 1.2us

08:45 <whitequark> okay, please correct it so that it adheres to the problem domain. I just ran the test

08:45 <whitequark> I never really figured out what kind of pulses does the test produce, I just made it faster...

08:51 <bb-m-labs> build #365 of artiq-kc705-nist_clock is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-kc705-nist_clock/builds/365

08:57 <bb-m-labs> build #140 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/140

08:59 <bb-m-labs> build #626 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/626

12:19 <cr1901_modern> sb0: Sent a patch for migen that I meant to do months ago. It improves Windoze behavior when building bitstreams. As always, please let me know if there's any problems when you get the chance.

15:29 <GitHub81> [artiq] sbourdeauducq pushed 1 new commit to release-1: https://git.io/vw4b2

15:29 <GitHub81> artiq/release-1 8a28039 whitequark: coredevice: deserialize int64(width=64) as int(width=64), not host_int....

16:52 <sb0> cr1901_modern, why not remove the epilogue and simply do "|| EXIT /B %errorlevel%" after each command?

16:56 <cr1901_modern> sb0: Yes, that would be a better idea. "|| exit /b" also works, according to this SO answer: http://stackoverflow.com/a/21912169